3.4.2. TX and RX Reference Clock and Clock Output Interface Signals

F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

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Date 11/04/2024

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3.4.2. TX and RX Reference Clock and Clock Output Interface Signals

Table 47. TX and RX Reference Clock and Clock Output Interface SignalsRefer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for variable definitions.
Signal Name	Clocks Domain/Resets	Direction	Description
`rx_clkout[(NX)-1:0]` `rx_clkout2[(NX)-1:0]]` `tx_clkout[(NX)-1:0]` `tx_clkout2[(NX)-1:0]`	N/A	output	Refer to Clock Ports Note: It is recommended to always use bit[0] to drive `tx_coreclkin[NX-1:0]` and `rx_coreclkin[NX-1:0]`. When `X` is larger than 1, bit [((`n`+1)`X`)-1: (`n``X`)+1] does not have valid output and must not be used. For example, when PMA width = 64, `X` = 2: If `N`=1, `n`=0: bit 1 does not have valid output and must not be used. If `N`=8, `n`=0 to 7: bits 1, 3, 5, 7, 9, 11, 13, 15 do not have valid output and must not be used. when PMA width = 128, `X` = 4: If `N`=1, `n`=0: bits 1, 2, 3 do not have valid output and must not be used. If `N`=4, `n`=0 to 3: bits 1, 2, 3, 5, 6, 7, 9, 10, 11, 13, 14, 15 do not have valid output and must not be used.
`tx_coreclkin[N*X-1:0]`	N/A	input	The FPGA core clock. Drives the write side of the TX FIFO.
`rx_coreclkin[N*X-1:0]`	N/A	input	The FPGA core clock. Drives the read side of the RX FIFO.
`tx_pll_refclk_link[N-1:0]` ²⁶ Note: This signal is single bit when Enable TX FGT PLL cascade mode is enabled.	N/A	input	This is neither physical nor logical pin. You connect this to <`out_refclk_fgt_<X>` > port from the F-Tile Reference and System PLL Clocks Intel® FPGA IP ²⁷. The N-bit ports must connect to the same source.
`rx_cdr_refclk_link[N-1:0]` Note: This signal is not available when Enable TX FGT PLL cascade mode is enabled.	N/A	input	This is neither physical nor logical pin. You connect this to <`out_refclk_fgt_<X>` > port from the F-Tile Reference and System PLL Clocks Intel® FPGA IP ²⁷. The N-bit ports must connect to the same source.
`system_pll_clk_link`	N/A	input	This is neither physical nor logical pin. You connect this to <`out_systempll_clk_0` > port from the F-Tile Reference and System PLL Clocks Intel® FPGA IP ²⁷.
`tx_pll_locked[N-1:0]`	asynchronous	output	For FGT and FHT PMA TX PLLs, this signal is sticky. Once asserted, this signal does not deassert regardless of the lock state of the TX PLL until either the TX channel is reset (for FGT PMAs) or the device is reconfigured (for FHT PMAs). This signal goes high under two conditions: TX PLL achieves lock to the reference clock when the reference clock is within the PPM threshold. In the presence of a reference clock, after approximately 150 µs (microsecond). `1’b1`: The TX PLL has achieved lock at least once or, in the presence of a reference clock, after approximately 150 µs. `1’b0`: The TX PLL has never achieved lock and, in the presence of a reference clock, approximately 150 µs have not been reached. To check the actual TX PLL locked state, Altera recommends following the Avalon® Memory-Mapped sequences provided in the Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs section.
`rx_cdr_divclk_link0`	N/A	output	Clock output from FGT CDR divided clock. This signal is used for CPRI. F-tile includes a total of two such pins. This port is neither physical nor logical pin. If you enable, you must set the number of system copies to 1. This port must connect to the `in_cdrclk_i` port of the F-Tile Reference and System PLL Clocks Intel® FPGA IP . This port cannot be enabled in a quad that has primary PLL configuration²⁷. This signal is not supported for FHT.

²⁶ Ports ending in "_link" must connect to the F-Tile Reference and System PLL Clocks Intel® FPGA IP. These ports cannot be simulated.

²⁷ Refer to Guidelines for F-Tile Reference and System PLL Clocks Intel FPGA IP Usage for reference clock and system PLL usage.