F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 11/04/2024
Public
Document Table of Contents

3.4.1. TX and RX Parallel and Serial Interface Signals

Table 46.  TX ad RX Paallel ad Seial Iteface SigalsRefe to Vaiables Defiig Bits fo the Itefacig Pots i Pot ad Sigal Refeece fo vaiable defiitios.
Sigal Name Clocks Domai/Resets Diectio Desciptio
tx_paallel_data [(80 * N * X)-1:0]

tx_coeclki

tx_eset

iput Paallel data bus fom FPGA coe to F-tile iteface. Some bits map to specific fuctioality, as Paallel Data Mappig Ifomatio descibes.
x_paallel_data[(80 * N * X) -1:0]

x_coeclki

x_eset

output Paallel data bus fom FPGA coe to F-tile iteface. Some bits map to specific fuctioality, as TX ad RX Paallel Data Mappig Ifomatio fo Diffeet Cofiguatios descibes.
tx_seial_data [N-1:0] tx_eset output TX seial data pot.
tx_seial_data_ [N-1:0] tx_eset output Diffeetial pai fo TX seial data pot.
x_seial_data [N-1:0] x_eset iput RX seial data pot.
x_seial_data_ [N-1:0] x_eset iput Diffeetial pai fo RX seial data pot.