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5.7. Simulating the F-Tile PMA/FEC Direct PHY Design
Simulation of the F-tile PMA/FEC Direct PHY design requires running the Quartus® Prime Compiler's Analysis & Elaboration and Support-Logic Generation stages to elaborate the component IP in your design. Next, you generate the simulator setup scripts for the Synopsys VCS* simulator, ModelSim* simulator, or any of the other supported simulation tools. You can modify and use the setup scripts to elaborate and simulate your design and testbench.
The simulation flow for F-tile differs from other serial interface tiles. The difference in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP simulation flow is that you cannot simulate individual IP files.
To simulate the F-tile PMA/FEC Direct PHY design:
- Click Processing > Start > Start Analysis & Elaboration. Review and correct any error messages.
- On the Compilation Dashboard, click Support-Logic Generation. Review and correct any error messages.
Note: A <top_level>_auto_tiles.sv file is auto-generated in the support_logic folder. For example, when the top-level entity is top, the generated file is top_auto_tiles.sv. For a Verilog or SystemVerilog test bench, you must instantiate this in your test bench. For a VHDL test bench, you must instantiate this in your top level entity.
- Click Tools > Generate Simulator Setup Script for IP and retain the default options. Ensure that you do not turn on the Use top-level entity names from Quartus project option.
Figure 111. Generate Simulator Setup Script for IP Dialog Box
- Click OK. Quartus® Prime Pro Edition software generates the <simulator_tool>_setup file in the <simulator_tool> directory and the <simulator_tool>_files.tcl files in the common directory, which is located in the Output directory path in step 3. The <simulator_tool>_setup file contains instructions for the simulation script file as well as any other simulation support files.
Note: To regenerate the <simulator tool>_setup file, repeat steps 3. and step 4. To regenerate the <simulator tool>_files.tcl, rename or delete the current version of the file and then repeat steps 3. and step 4.
- Navigate to the directory of the simulation tool you plan to use and open the <simulator_tool>_setup file.
Note: The Mentor Graphics* directory is for QuestaSim* .
- Review the instructions in the <simulator tool>_setup file to create a simulation script file based on the given template. The simulation script file contains the script you need to compile and run the testbench for a given simulator tool. The following shows an example of the vcs_sim.sh, the simulation script file for VCS* simulator. To view an example for other simulator tools, generate an example design for simulation with your desired simulation tool. Your simulation script content can vary based on your design characteristics.
source ./vcs_setup.sh \ TOP_LEVEL_NAME=top_tb \ QSYS_SIMDIR=../.. \ USER_DEFINED_ELAB_OPTIONS="\"-full64 +v2k -hsopt=gates \ +systemverilogext+.sv -sverilog -lca +lint=TFIPC-L +lint=PCWM -wreal res_def \ -xlrm coerce_nettype -timescale=1ns/1ps +vcs+vcdpluson +vpddrivers \ +define+TIMESCALE_EN +define+INTC_FUNCTIONAL +define+RTLSIM \ +define+SSM_SEQUENCE \ +define+IP7581SERDES_UXS2T1R1PGD_PIPE_SPEC_FORCE \ +define+IP7581SERDES_UXS2T1R1PGD_PIPE_SIMULATION \ +define+IP7581SERDES_UXS2T1R1PGD_PIPE_FAST_SIM +error+1000 \ +define+__SRC_TEST__ -debug_access+r+driver+f -debug_region+encrypt \ +rad -f ./filelist.f \" " \ USER_DEFINED_ELAB_OPTIONS_APPEND="\" -l vcs.log\" " ./simv +lic+wait -l simulation.log +fsdb+mda=on +fsdbfile+novas.fsdb
Note: The QSYS_SIMDIR must be the relative path to the directory you selected in step 3.Note:For a list of other Fast Sim macros available refer to the following knowledge base article (KDB):In order to provide a reduction in real-time simulation duration, you can use a Fast Sim model. This model is enabled via a macro in the simulation run scripts. The syntax to enable the Fast Sim model is as follows:
+define+IP7581SERDES_UX_SIMSPEED
Which Fast Simulation Macros are documented for the Agilex™ 7 F-Tile Hard IP?
- Create your test bench.
- For a Verilog or SystemVerilog test bench:
When calling the top level module in the test bench, the module name must be the same as instance name. For example:
top top ( ports passing );
A mismatch between the module and instance names causes errors during compilation. For example, the following produces errors during compilation:top top_instant0 ( ports passing );
Also be sure to add this instantiation in your test bench:top_auto_tiles <any names> ();
For example, <any names> can be top_auto_tiles_inst1. - For a VHDL test bench:
The module name must be different from the instance name. For example:
DUT_top: top port map ( ports passing );
Also be sure to add this instantiation in your top level entity:<different names>: top_auto_tiles ;
For example, <different names> can be DUT_top_auto_tiles.
- For a Verilog or SystemVerilog test bench:
- Create any other necessary support files as mentioned in the <simulator_tool>_setup file. For example, vcs_setup.sh contains the instructions for a file that contains a list of all design files and testbench files including the top-level that you require for simulation other than the files compiled by the Quartus® Prime Pro Edition software generated IP simulation script. In this example, the file is named filelist.f. However, the file name is arbitrary and you can be name it anything (for example, common_files_list.f). Note that the file location is relative to the vcs_sim.sh command. The following shows one example filelist.f. The content of this file can vary, depending on your design characteristics.
# # DESIGN FILE LIST & OPTIONS TEMPLATE - BEGIN # # # # Compile all design files and testbench files, including the top level. # # (These are all the files required for simulation other than the files # # compiled by the Quartus-generated IP simulation script) # # # +systemverilogext+.sv # <design and testbench files, compile-time options, elaboration options> # # # # DESIGN FILE LIST & OPTIONS TEMPLATE - END ../../top.v ../../top_tb.v
- Start your simulation tool and run compilation and simulation.
- Launch waveform viewer.
Table 116. Essential F-Tile Simulation Files File Name File Description <simulator tool>_setup Provides instructions to set up the simulation file and other supporting files, like common files list, as well as a script sourced by the simulation file. <simulator tool>_files.tcl Script to load design files, environment variables, and libraries. Note: Do not edit the Tcl file.Simulation script Your script to run simulations. Note: Make sure the local paths are correct.Common files list List of all design files and testbench files required for simulation.