F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

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ID 683872
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile Overview 2. F-Tile Architecture 3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5. F-Tile PMA/FEC Direct PHY Design Implementation 6. Supported Tools 7. Debugging F-Tile Transceiver Links 8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives 9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide A. Appendix
1. F-Tile Overview x
1.1. Device Family Support
2. F-Tile Architecture x
2.1. F-Tile Building Blocks 2.2. F-Tile Placement Rules 2.3. PMA Architecture 2.4. Clock Architecture
2.1. F-Tile Building Blocks x
2.1.1. FHT and FGT PMAs 2.1.2. 400G Hard IP and 200G Hard IP 2.1.3. PMA Data Rates 2.1.4. FEC Architecture 2.1.5. PCIe* Hard IP 2.1.6. Bonding Architecture 2.1.7. Deskew Logic 2.1.8. Embedded Multi-die Interconnect Bridge (EMIB) 2.1.9. IEEE 1588 Precision Time Protocol for Ethernet 2.1.10. Clock Networks 2.1.11. Reconfiguration Interfaces
2.2. F-Tile Placement Rules x
2.2.1. PMA-to-Fracture Mapping 2.2.2. Determining Which PMA to Map to Which Fracture 2.2.3. Hard IP Placement Rules 2.2.4. IEEE 1588 Precision Time Protocol Placement Rules 2.2.5. Topologies 2.2.6. FEC Placement Rules 2.2.7. Clock Rules and Restrictions 2.2.8. Bonding Placement Rules 2.2.9. Preserving Unused PMA Lanes
2.2.1. PMA-to-Fracture Mapping x
2.2.1.1. FHT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.2. FGT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.3. FGT-PMA-to-200G-Hard-IP-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture x
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT 2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT 2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT 2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT 2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT 2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
2.2.5. Topologies x
2.2.5.1. Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) Example 2.2.5.2. Topology 6a: 400G Hard IP with Mixed Transceiver Mode Example 2.2.5.3. Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP Example
2.2.8. Bonding Placement Rules x
2.2.8.1. Bonded Lanes Use Case 1 2.2.8.2. Bonded Lanes Use Case 2
2.3. PMA Architecture x
2.3.1. FHT PMA Architecture 2.3.2. FGT PMA Architecture
2.3.1. FHT PMA Architecture x
2.3.1.1. FHT Transmitter PMA Architecture 2.3.1.2. FHT Receiver PMA Architecture 2.3.1.3. FHT PMA Loopback Modes
2.3.1.1. FHT Transmitter PMA Architecture x
2.3.1.1.1. FHT Transmitter Buffer and Phase Generator 2.3.1.1.2. FHT Serializer 2.3.1.1.3. FHT Gray-Coder and Pre-Coder 2.3.1.1.4. FHT Data Pattern Generator and Verifier
2.3.1.2. FHT Receiver PMA Architecture x
2.3.1.2.1. FHT Receiver Buffer and Equalizer 2.3.1.2.2. CDR Block 2.3.1.2.3. FHT Deserializer
2.3.2. FGT PMA Architecture x
2.3.2.1. FGT Transmitter PMA Architecture 2.3.2.2. FGT Receiver PMA Architecture 2.3.2.3. FGT PMA Tuning 2.3.2.4. FGT PMA Loopback Modes
2.3.2.1. FGT Transmitter PMA Architecture x
2.3.2.1.1. FGT Transmitter Buffer and Phase Generator 2.3.2.1.2. FGT Serializer 2.3.2.1.3. FGT Gray-Coder and Pre-Coder 2.3.2.1.4. FGT Data Pattern Generator and Verifier
2.3.2.2. FGT Receiver PMA Architecture x
2.3.2.2.1. FGT Receiver Buffer and Equalizer 2.3.2.2.2. Control Unit 2.3.2.2.3. FGT Deserializer
2.4. Clock Architecture x
2.4.1. Reference Clock Network 2.4.2. Datapath Clock Network 2.4.3. System PLL 2.4.4. Datapath Clock Cadences
2.4.1. Reference Clock Network x
2.4.1.1. FHT Reference Clock Network 2.4.1.2. FGT and System PLL Reference Clock Network 2.4.1.3. FGT Primary PLL Configuration
2.4.1.2. FGT and System PLL Reference Clock Network x
2.4.1.2.1. FGT Reference Clock Receiver Analog Front End
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview 3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.3. Configuring the IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting Reset 3.9. Bonding Implementation 3.10. Independent Port Configurations 3.11. Configuration Registers 3.12. Configurable Quartus® Prime Software Settings 3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. Unsupported PMA/FEC Modes
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.2.1. Preset IP Parameter Settings
3.3. Configuring the IP x
3.3.1. General and Common Datapath Options 3.3.2. TX Datapath Options 3.3.3. RX Datapath Options 3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options 3.3.5. Avalon® Memory Mapped Interface Options 3.3.6. Register Map IP-XACT Support 3.3.7. Example Design Generation 3.3.8. Analog Parameter Options
3.3.1. General and Common Datapath Options x
3.3.1.1. FGT PMA Configuration Rules for SATA mode 3.3.1.2. FGT PMA Configuration Rules for GPON Mode
3.3.2. TX Datapath Options x
3.3.2.1. TX PMA interface Parameters
3.3.3. RX Datapath Options x
3.3.3.1. RX FGT PMA Interface Options
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. RS-FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. TX PMA Control Signals 3.4.7. RX PMA Status Signals 3.4.8. TX and RX PMA and Core Interface FIFO Signals 3.4.9. PMA Avalon® Memory Mapped Interface Signals 3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals x
3.4.10.1. Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per Interface
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath x
3.5.1. Parallel Data Mapping Information 3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations 3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1) 3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2) 3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations x
3.5.2.1. TX Parallel Data Mapping Information for SATA Protocol Mode for Different Configurations
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. FGT PMA Fractional Mode 3.6.5. FGT RX CDR Clock Output
3.6.5. FGT RX CDR Clock Output x
3.6.5.1. Dynamically Configure the FGT RX CDR Clock Output
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the tx_cadence_slow_clk_locked Port 3.7.2. Rate Match FIFO
3.8. Asserting Reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Reset Signals—Descriptions 3.8.5. Status Signals—Descriptions 3.8.6. Run-time Reset Sequence—TX 3.8.7. Run-time Reset Sequence—RX 3.8.8. Run-time Reset Sequence—TX + RX 3.8.9. Run-time Reset Sequence—TX with FEC
3.8.8. Run-time Reset Sequence—TX + RX x
3.8.8.1. Run-time Reset Sequence Approximate Time Durations
3.11. Configuration Registers x
3.11.1. PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. FHT PMA Register Map 3.11.3. FGT PMA Register Map 3.11.4. FEC Register Map 3.11.5. Lane Offset Address 3.11.6. Accessing Configuration Registers
3.11.6. Accessing Configuration Registers x
3.11.6.1. Accessing PMA and FEC Direct PHY Soft CSR Registers 3.11.6.2. Accessing FHT PMA Registers 3.11.6.3. Accessing FGT PMA Registers
3.11.6.2. Accessing FHT PMA Registers x
3.11.6.2.1. FHT PMA Register Address Range 0x40000 to 0x48000 3.11.6.2.2. FHT PMA Register Address Range 0x60000 to 0xF0030 3.11.6.2.3. FHT PMA Register Address 0xFFFFC
3.11.6.3. Accessing FGT PMA Registers x
3.11.6.3.1. FGT PMA Register Address Range 0x40000 to 0x48000 3.11.6.3.2. FGT PMA Register Address Range 0x62000 to 0x62004 3.11.6.3.3. FGT PMA Register Address Range 0x9003C to 0xF0028 3.11.6.3.4. FGT PMA Register Address 0xFFFFC
3.12. Configurable Quartus® Prime Software Settings x
3.12.1. FHT PMA Settings 3.12.2. FGT PMA Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing x
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.13.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP x
3.13.2.1. RTL Connection Example for JTAG to Avalon® Master Bridge Intel IP
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. FHT PMA 3.14.2. FGT PMA
3.14.1. FHT PMA x
3.14.1.1. Enabling Loopback 3.14.1.2. Enabling the PRBS Generator and Verifier for ES Devices Obtaining BER Values for Production Devices 3.14.1.4. TX Equalizer Settings 3.14.1.5. TX Error Injection 3.14.1.6. RX Reconvergence 3.14.1.7. Preserving Unused Lanes
3.14.2. FGT PMA x
3.14.2.1. Direct Register Method 3.14.2.2. FGT Attribute Access Method
3.14.2.1. Direct Register Method x
3.14.2.1.1. Direct Register Method Examples
3.14.2.2. FGT Attribute Access Method x
3.14.2.2.1. FGT Attribute Access Method Example 1 3.14.2.2.2. FGT Attribute Access Method Example 2 3.14.2.2.3. FGT Attribute Access Method Example 3
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for F-Tile Reference and System PLL Clocks Intel® FPGA IP Usage 4.5. Guidelines for Refclk #i is Active At and After Device Configuration 4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs
4.5. Guidelines for Refclk #i is Active At and After Device Configuration x
4.5.1. Guidelines for System PLL Reference Clock 4.5.2. Guidelines for FGT Reference Clock
4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs x
4.6.1. How to Read the Real-Time Lock Status of the FGT TX PLL 4.6.2. How to Read the Real-Time Lock Status of the FHT Lane TX PLL 4.6.3. How to Read the Real-Time Lock Status of the FHT Common TX PLL 4.6.4. How to Reset the FGT TX PLL 4.6.5. How to Reset the FHT Lane TX PLL and Common PLL
4.6.1. How to Read the Real-Time Lock Status of the FGT TX PLL x
4.6.1.1. How to Determine the TX PLL Your FGT Channel is Using
4.6.3. How to Read the Real-Time Lock Status of the FHT Common TX PLL x
4.6.3.1. How to Determine Which Common PLL Your FHT Channel is Using
5. F-Tile PMA/FEC Direct PHY Design Implementation x
5.1. Implementing the F-Tile PMA/FEC Direct PHY Design 5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5.5. Enabling Custom Cadence Generation Ports and Logic 5.6. Connecting the F-Tile PMA/FEC Direct PHY Design IP 5.7. Simulating the F-Tile PMA/FEC Direct PHY Design 5.8. F-Tile Interface Planning
5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
5.2.1. Setting General and Common Datapath Options 5.2.2. Setting TX Datapath Options 5.2.3. Setting RX Datapath Options
5.7. Simulating the F-Tile PMA/FEC Direct PHY Design x
5.7.1. PAM4 Encoding Schemes in Simulation
5.8. F-Tile Interface Planning x
5.8.1. F-Tile Interface Planner Usage Example
6. Supported Tools x
6.1. F-Tile Channel Placement Tool 6.2. F-Tile PMA and FEC Direct Port Mapping Calculator 6.3. F-Tile Clocking and Datapath Tool 6.4. F-Tile FGT TX Equalizer Tool
7. Debugging F-Tile Transceiver Links x
7.1. F-Tile Transceiver Toolkit GUI 7.2. F-Tile Transceiver Debugging Flow Walkthrough 7.3. Transceiver Toolkit Parameter Settings 7.4. Using F-Tile Multirate IPs with Transceiver Toolkit 7.5. Troubleshooting Common Errors 7.6. Transceiver Toolkit Scripts
7.1. F-Tile Transceiver Toolkit GUI x
7.1.1. Collection View
7.2. F-Tile Transceiver Debugging Flow Walkthrough x
7.2.1. Modifying the Design to Enable F-Tile Transceiver Debug 7.2.2. Programming the Design into an Intel FPGA 7.2.3. Loading the Design to the Transceiver Toolkit 7.2.4. Creating Transceiver Links 7.2.5. Running BER Tests 7.2.6. Running Eye Viewer Tests 7.2.7. Running Link Optimization Tests 7.2.8. Checking FEC Statistics 7.2.9. Vertical Bathtub Curve Measurements (VBCM) Data
7.3. Transceiver Toolkit Parameter Settings x
7.3.1. Dashboard
7.4. Using F-Tile Multirate IPs with Transceiver Toolkit x
7.4.1. F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP 7.4.2. F-Tile Ethernet Multirate Intel FPGA IP 7.4.3. Ethernet Subsystem Intel FPGA IP
7.6. Transceiver Toolkit Scripts x
7.6.1. Supported Transceiver Toolkit Scripts 7.6.2. Modifying the Scripts 7.6.3. Script Execution 7.6.4. Example of the Results in Tcl Console
A. Appendix x
A.1. Agilex™ 7 F-Tile OPNs A.2. OSC_CLK_1 QSF Assignment Requirement A.3. FGT Internal Serial Loopback Calibration Sequence for RX Manual Adaptation
1. F-Tile Overview
2. F-Tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. F-Tile PMA/FEC Direct PHY Design Implementation
6. Supported Tools
7. Debugging F-Tile Transceiver Links
8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide
A. Appendix

3.3.3. RX Datapath Options

Figue 66. RX Datapath Optios i Paamete Edito
Table 34.  RX FGT PMA Paametes
Paamete Values Desciptio
Eable Gay codig O/Off Eables Gay codig.

I PAM4 mode, gay codig is eabled by default ad you caot disable it i the paamete edito GUI. Default value is O. You ca disable gay codig though a egiste wite.

I NRZ mode, gay codig is disabled by default ad you caot eable it. Default is Off.

Eable pecodig O/Off Eables pecodig. Applicable to PAM4 ecodig oly. Default value is Off.
PRBS moito mode 25 disable, PRBS7, PRBS9, PRBS10, PRBS13, PRBS15, PRBS23, PRBS28, PRBS31, QPRBS13, PRBS13Q, PRBS31Q, SSPR, SSPR1, SSPRQ Eables had PRBS geeato with the PRBS polyomial selectio. Default value is disable.
Eable SATA squelch detectio O/Off Eables squelch detectio fo SATA. Default value is Off.
Eable fgt_x_sigal_detect pot O/Off Eables the fgt_x_sigal_detect pot. This pot is used fo SATA potocol mode fo out of bad (OOB) sigal detectio. Default value is Off.
Eable fgt_x_sigal_detect_lfps pot O/Off Eables the fgt_x_sigal_detect_lfps pot. This pot is used fo SATA potocol mode fo low fequecy peiodic sigalig (LFPS) sigal detectio. Default value is Off.
Eable x_cd_divclk_lik0 pot O/Off Eables the lik pot epesetig RX CDR clock output fom RX PMA to the efeece clock pi. The coectio made fom this pot to the F-Tile Refeece ad System PLL Clocks Itel® FPGA IP guides the Fitte to detemie the physical pi. Do ot use this pi itself i simulatio to obseve clock behavio. Obseve the actual clock behavio i the elated output pot of the F-Tile Refeece ad System PLL Clocks Itel® FPGA IP. The physical pot is typically used fo CPRI. You ca coect the physical pot to the physical efeece clock pi 8 o 9 fo cofiguatio as RX CDR clock output. This settig is applicable fo FGT PMA oly. Default value is Off.
Selected x_cd_divclk_lik0 souce 0 to mi(7, N-1), (N = Numbe of PMA Laes) Detemies which RX FGT PMA lae is soucig fgt_x_cd_divclk_lik0. Note that FGT PMA idex used i this paamete is logical. The selected PMA lae must be physically mapped to FGT Quad 3 (with efeece clock 9) o FGT Quad 2 (with efeece clock 8). If Eable x_cd_divclk_lik0 pot is off, this paamete is igoed. Default value is Off.
Adaptatio mode

auto,

maual

I maual mode, you must povide the aalog fot ed settigs: RXEQ VGA Gai, RXEQ High Fequecy Boost, ad RXEQ DFE Data Tap 1. You must ete the iitializatio values fo these settigs ude the Aalog Paametes tab. You ca also dyamically cofigue these settigs by accessig the FGT PMA egistes. I auto mode, the PMA adjusts the aalog fot ed settigs automatically. Default value is auto.
Eable fgt_x_cd_fast_feeze_sel pot O/Off This pot is used fo GPON. Fo GPON mode, you must eable ad tie the fgt_x_cd_fast_feeze_sel sigal to 1'b0. It allows fgt_x_cd_feeze cotol sigal to popagate coectly. Default value is Off.
Eable fgt_x_cd_set_locktoef pot O/Off Pimaily used fo GPON. This sigal oly takes effect whe FGT PMA cofiguatio ules is set to GPON, Adaptatio mode is set to maual, ad CDR lock mode is set to auto. Whe eabled, assetig the fgt_x_cd_set_locktoef sigal keeps the CDR i maual lock-to-efeece mode. Deassetig this sigal keeps CDR i maual lock-to-data mode. I maual lock-to-efeece mode, you must otify the eset cotolle to igoe the lock to data status by settig the soft CSR egiste 0x818[0] to 1'b1. Default value is Off.
RX FGT CDR Settigs
Output fequecy 12890.625MHz Specifies the o editable RX FGT CDR output fequecy iitial value deived fom the IP cofiguatio.
VCO fequecy 12890.625MHz Specifies the o editable RX FGT CDR VCO output fequecy iitial value deived fom the IP cofiguatio.
RX FGT CDR efeece clock fequecy 25.781250-250.000000 Selects the efeece clock fequecy (MHz) fo CDR. Default value is 156.25.
CDR lock mode

auto,

maual lock to efeece

Whe auto is selected, duig use iitiated eset o powe-up, CDR fist ties to lock to efeece ad the locks to data if peset. By default, loss of lock to data e-tigges eset RX PMA eset. Whe maual lock to efeece is selected, you must dive fgt_x_set_locktoef to cotol the CDR lock behavio. Default value is auto.
Eable fgt_x_set_locktoef pot O/Off You must eable this pot whe CDR lock mode is set to maual lock to efeece. This sigal oly takes effect whe Adaptatio mode is set to maual. Assetig this sigal keeps CDR i maual mode. Deassetig this sigal keeps CDR i auto mode. Whe switchig modes, you must asset x_eset. I maual mode, you must otify the eset cotolle to igoe lock to data status by settig soft CSR egiste 0x818[0] to 1'b1. Default value is Off.
Eable fgt_x_set_locktodata pot O/Off You must eable this pot whe CDR lock mode is set to maual lock to efeece. This sigal oly takes effect whe Adaptatio mode is set to maual, fgt_x_set_locktoef is asseted, ad CDR is i maual mode. Assetig this sigal keeps CDR i maual lock-to-data mode. Deassetig this sigal keeps CDR i maual lock-to-efeece mode, which is used fo ovesamplig applicatios. Default value is Off.
Eable fgt_x_cd_feeze pot O/Off

This pot is used fo GPON to feeze the CDR lock state duig o-active time slots. Default value is Off.

RX Use Clock Settig
Eable RX use clock O/Off Divide values of RX CDR output fequecy. If the clock is ot used, you ca disable the clock to save powe. This clock souce dives both RX Use Clock1 ad Use Clock 2 i the Coe Iteface. Default value is Off.
RX use clock div by 12- 139.5 Divisio facto fom Fvco of RX CDR to RX use clock. Values fom 12 to 139.5 ae acceptable i 0.5 icemets. Default value is 100.
Figue 67. RX FHT PMA Paametes i Paamete Edito
Table 35.  RX FHT PMA Paametes
Paamete Values Desciptio
Eable FHT RX PAM4 Level Alteative Codig O/Off Eable this fo RX PAM4 Level Alteative Codig. Whe disabled, lik pate must sed gay code set to 0xB4. Whe eabled, lik pate must sed gay code set to 0x6C. You must disable this paamete fo omal opeatio o whe i iteal o exteal loopback. Default value is Off.
Eable FHT RX data pofile Disabled/Eabled Eable FHT RX data pofile to set the theshold fo umbe of 1’s i 1M RX Data bits that detemie the quality of RX data. If the umbe of 1's eceived is ot withi the specified mi ad max theshold, the RX bad status is idicated. Default is Eabled.
Note: This paamete must be Eabled.
FHT RX use clk div33_34 select

RX_DIV_33

RX_DIV_34

RX_DIV_66

RX_DIV_68

Selects oe of the fou DIV clock output fo the RX use clock. Refe to Clockig. Default is RX_DIV_66.
Eable FHT RX pe-ecode O/Off Eables FHT TX pe-ecode. Default value is off. This settig must match the lik pate's RX pe-ecode settig. Default value is Off.
Eable FHT RX use clk1 O/Off Eables FHT RX use clk1. Default is Off.
FHT RX use clk1 select

DIV3334

DIV40

FHT RX use clk1 select. Off selects div3334 (oe of the fou DIV clocks listed i use div33_34). O selects DIV40 clock. Refe to Clockig. Default is div3334.
Eable FHT RX use clk2 O/Off Eables FHT RX use clk2. Default value is Off.
FHT RX use clk2 select

DIV3334

DIV40

FHT RX use clk2 select. Off selects div3334 (oe of the fou DIV clocks listed i use div33_34). O selects DIV40 clock. Refe to Clockig. Default is div3334.

Sectio Cotet
RX FGT PMA Iteface Optios

25

The PRBS31, QPRBS13, PRBS13Q, PRBS31Q, SSPR, SSPR1, ad SSPRQ PRBS geeato mode settigs ae ot cuetly suppoted though the IP GUI, although peset i the paamete edito. Do ot select ay of the usuppoted PRBS geeato mode settigs. Specify these settigs usig egistes.

Level Two Title