F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

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ID 683872
Date 11/04/2024
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Document Table of Contents
Document Table of Contents x
1. F-Tile Overview 2. F-Tile Architecture 3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5. F-Tile PMA/FEC Direct PHY Design Implementation 6. Supported Tools 7. Debugging F-Tile Transceiver Links 8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives 9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide A. Appendix
1. F-Tile Overview x
1.1. Device Family Support
2. F-Tile Architecture x
2.1. F-Tile Building Blocks 2.2. F-Tile Placement Rules 2.3. PMA Architecture 2.4. Clock Architecture
2.1. F-Tile Building Blocks x
2.1.1. FHT and FGT PMAs 2.1.2. 400G Hard IP and 200G Hard IP 2.1.3. PMA Data Rates 2.1.4. FEC Architecture 2.1.5. PCIe* Hard IP 2.1.6. Bonding Architecture 2.1.7. Deskew Logic 2.1.8. Embedded Multi-die Interconnect Bridge (EMIB) 2.1.9. IEEE 1588 Precision Time Protocol for Ethernet 2.1.10. Clock Networks 2.1.11. Reconfiguration Interfaces
2.2. F-Tile Placement Rules x
2.2.1. PMA-to-Fracture Mapping 2.2.2. Determining Which PMA to Map to Which Fracture 2.2.3. Hard IP Placement Rules 2.2.4. IEEE 1588 Precision Time Protocol Placement Rules 2.2.5. Topologies 2.2.6. FEC Placement Rules 2.2.7. Clock Rules and Restrictions 2.2.8. Bonding Placement Rules 2.2.9. Preserving Unused PMA Lanes
2.2.1. PMA-to-Fracture Mapping x
2.2.1.1. FHT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.2. FGT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.3. FGT-PMA-to-200G-Hard-IP-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture x
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT 2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT 2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT 2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT 2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT 2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
2.2.5. Topologies x
2.2.5.1. Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) Example 2.2.5.2. Topology 6a: 400G Hard IP with Mixed Transceiver Mode Example 2.2.5.3. Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP Example
2.2.8. Bonding Placement Rules x
2.2.8.1. Bonded Lanes Use Case 1 2.2.8.2. Bonded Lanes Use Case 2
2.3. PMA Architecture x
2.3.1. FHT PMA Architecture 2.3.2. FGT PMA Architecture
2.3.1. FHT PMA Architecture x
2.3.1.1. FHT Transmitter PMA Architecture 2.3.1.2. FHT Receiver PMA Architecture 2.3.1.3. FHT PMA Loopback Modes
2.3.1.1. FHT Transmitter PMA Architecture x
2.3.1.1.1. FHT Transmitter Buffer and Phase Generator 2.3.1.1.2. FHT Serializer 2.3.1.1.3. FHT Gray-Coder and Pre-Coder 2.3.1.1.4. FHT Data Pattern Generator and Verifier
2.3.1.2. FHT Receiver PMA Architecture x
2.3.1.2.1. FHT Receiver Buffer and Equalizer 2.3.1.2.2. CDR Block 2.3.1.2.3. FHT Deserializer
2.3.2. FGT PMA Architecture x
2.3.2.1. FGT Transmitter PMA Architecture 2.3.2.2. FGT Receiver PMA Architecture 2.3.2.3. FGT PMA Tuning 2.3.2.4. FGT PMA Loopback Modes
2.3.2.1. FGT Transmitter PMA Architecture x
2.3.2.1.1. FGT Transmitter Buffer and Phase Generator 2.3.2.1.2. FGT Serializer 2.3.2.1.3. FGT Gray-Coder and Pre-Coder 2.3.2.1.4. FGT Data Pattern Generator and Verifier
2.3.2.2. FGT Receiver PMA Architecture x
2.3.2.2.1. FGT Receiver Buffer and Equalizer 2.3.2.2.2. Control Unit 2.3.2.2.3. FGT Deserializer
2.4. Clock Architecture x
2.4.1. Reference Clock Network 2.4.2. Datapath Clock Network 2.4.3. System PLL 2.4.4. Datapath Clock Cadences
2.4.1. Reference Clock Network x
2.4.1.1. FHT Reference Clock Network 2.4.1.2. FGT and System PLL Reference Clock Network 2.4.1.3. FGT Primary PLL Configuration
2.4.1.2. FGT and System PLL Reference Clock Network x
2.4.1.2.1. FGT Reference Clock Receiver Analog Front End
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview 3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.3. Configuring the IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting Reset 3.9. Bonding Implementation 3.10. Independent Port Configurations 3.11. Configuration Registers 3.12. Configurable Quartus® Prime Software Settings 3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. Unsupported PMA/FEC Modes
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.2.1. Preset IP Parameter Settings
3.3. Configuring the IP x
3.3.1. General and Common Datapath Options 3.3.2. TX Datapath Options 3.3.3. RX Datapath Options 3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options 3.3.5. Avalon® Memory Mapped Interface Options 3.3.6. Register Map IP-XACT Support 3.3.7. Example Design Generation 3.3.8. Analog Parameter Options
3.3.1. General and Common Datapath Options x
3.3.1.1. FGT PMA Configuration Rules for SATA mode 3.3.1.2. FGT PMA Configuration Rules for GPON Mode
3.3.2. TX Datapath Options x
3.3.2.1. TX PMA interface Parameters
3.3.3. RX Datapath Options x
3.3.3.1. RX FGT PMA Interface Options
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. RS-FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. TX PMA Control Signals 3.4.7. RX PMA Status Signals 3.4.8. TX and RX PMA and Core Interface FIFO Signals 3.4.9. PMA Avalon® Memory Mapped Interface Signals 3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals x
3.4.10.1. Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per Interface
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath x
3.5.1. Parallel Data Mapping Information 3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations 3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1) 3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2) 3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations x
3.5.2.1. TX Parallel Data Mapping Information for SATA Protocol Mode for Different Configurations
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. FGT PMA Fractional Mode Tuig the k Coute Value i Factioal Mode 3.6.5. FGT RX CDR Clock Output
3.6.5. FGT RX CDR Clock Output x
3.6.5.1. Dynamically Configure the FGT RX CDR Clock Output
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the tx_cadence_slow_clk_locked Port 3.7.2. Rate Match FIFO
3.8. Asserting Reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Reset Signals—Descriptions 3.8.5. Status Signals—Descriptions 3.8.6. Run-time Reset Sequence—TX 3.8.7. Run-time Reset Sequence—RX 3.8.8. Run-time Reset Sequence—TX + RX 3.8.9. Run-time Reset Sequence—TX with FEC
3.8.8. Run-time Reset Sequence—TX + RX x
3.8.8.1. Run-time Reset Sequence Approximate Time Durations
3.11. Configuration Registers x
3.11.1. PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. FHT PMA Register Map 3.11.3. FGT PMA Register Map 3.11.4. FEC Register Map 3.11.5. Lane Offset Address 3.11.6. Accessing Configuration Registers
3.11.6. Accessing Configuration Registers x
3.11.6.1. Accessing PMA and FEC Direct PHY Soft CSR Registers 3.11.6.2. Accessing FHT PMA Registers 3.11.6.3. Accessing FGT PMA Registers
3.11.6.2. Accessing FHT PMA Registers x
3.11.6.2.1. FHT PMA Register Address Range 0x40000 to 0x48000 3.11.6.2.2. FHT PMA Register Address Range 0x60000 to 0xF0030 3.11.6.2.3. FHT PMA Register Address 0xFFFFC
3.11.6.3. Accessing FGT PMA Registers x
3.11.6.3.1. FGT PMA Register Address Range 0x40000 to 0x48000 3.11.6.3.2. FGT PMA Register Address Range 0x62000 to 0x62004 3.11.6.3.3. FGT PMA Register Address Range 0x9003C to 0xF0028 3.11.6.3.4. FGT PMA Register Address 0xFFFFC
3.12. Configurable Quartus® Prime Software Settings x
3.12.1. FHT PMA Settings 3.12.2. FGT PMA Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing x
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.13.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP x
3.13.2.1. RTL Connection Example for JTAG to Avalon® Master Bridge Intel IP
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. FHT PMA 3.14.2. FGT PMA
3.14.1. FHT PMA x
3.14.1.1. Enabling Loopback 3.14.1.2. Enabling the PRBS Generator and Verifier for ES Devices Obtaining BER Values for Production Devices 3.14.1.4. TX Equalizer Settings 3.14.1.5. TX Error Injection 3.14.1.6. RX Reconvergence 3.14.1.7. Preserving Unused Lanes
3.14.2. FGT PMA x
3.14.2.1. Direct Register Method 3.14.2.2. FGT Attribute Access Method
3.14.2.1. Direct Register Method x
3.14.2.1.1. Direct Register Method Examples
3.14.2.2. FGT Attribute Access Method x
3.14.2.2.1. FGT Attribute Access Method Example 1 3.14.2.2.2. FGT Attribute Access Method Example 2 3.14.2.2.3. FGT Attribute Access Method Example 3
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for F-Tile Reference and System PLL Clocks Intel® FPGA IP Usage 4.5. Guidelines for Refclk #i is Active At and After Device Configuration 4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs
4.5. Guidelines for Refclk #i is Active At and After Device Configuration x
4.5.1. Guidelines for System PLL Reference Clock 4.5.2. Guidelines for FGT Reference Clock
4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs x
4.6.1. How to Read the Real-Time Lock Status of the FGT TX PLL 4.6.2. How to Read the Real-Time Lock Status of the FHT Lane TX PLL 4.6.3. How to Read the Real-Time Lock Status of the FHT Common TX PLL 4.6.4. How to Reset the FGT TX PLL 4.6.5. How to Reset the FHT Lane TX PLL and Common PLL
4.6.1. How to Read the Real-Time Lock Status of the FGT TX PLL x
4.6.1.1. How to Determine the TX PLL Your FGT Channel is Using
4.6.3. How to Read the Real-Time Lock Status of the FHT Common TX PLL x
4.6.3.1. How to Determine Which Common PLL Your FHT Channel is Using
5. F-Tile PMA/FEC Direct PHY Design Implementation x
5.1. Implementing the F-Tile PMA/FEC Direct PHY Design 5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5.5. Enabling Custom Cadence Generation Ports and Logic 5.6. Connecting the F-Tile PMA/FEC Direct PHY Design IP 5.7. Simulating the F-Tile PMA/FEC Direct PHY Design 5.8. F-Tile Interface Planning
5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
5.2.1. Setting General and Common Datapath Options 5.2.2. Setting TX Datapath Options 5.2.3. Setting RX Datapath Options
5.7. Simulating the F-Tile PMA/FEC Direct PHY Design x
5.7.1. PAM4 Encoding Schemes in Simulation
5.8. F-Tile Interface Planning x
5.8.1. F-Tile Interface Planner Usage Example
6. Supported Tools x
6.1. F-Tile Channel Placement Tool 6.2. F-Tile PMA and FEC Direct Port Mapping Calculator 6.3. F-Tile Clocking and Datapath Tool 6.4. F-Tile FGT TX Equalizer Tool
7. Debugging F-Tile Transceiver Links x
7.1. F-Tile Transceiver Toolkit GUI 7.2. F-Tile Transceiver Debugging Flow Walkthrough 7.3. Transceiver Toolkit Parameter Settings 7.4. Using F-Tile Multirate IPs with Transceiver Toolkit 7.5. Troubleshooting Common Errors 7.6. Transceiver Toolkit Scripts
7.1. F-Tile Transceiver Toolkit GUI x
7.1.1. Collection View
7.2. F-Tile Transceiver Debugging Flow Walkthrough x
7.2.1. Modifying the Design to Enable F-Tile Transceiver Debug 7.2.2. Programming the Design into an Intel FPGA 7.2.3. Loading the Design to the Transceiver Toolkit 7.2.4. Creating Transceiver Links 7.2.5. Running BER Tests 7.2.6. Running Eye Viewer Tests 7.2.7. Running Link Optimization Tests 7.2.8. Checking FEC Statistics 7.2.9. Vertical Bathtub Curve Measurements (VBCM) Data
7.3. Transceiver Toolkit Parameter Settings x
7.3.1. Dashboard
7.4. Using F-Tile Multirate IPs with Transceiver Toolkit x
7.4.1. F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP 7.4.2. F-Tile Ethernet Multirate Intel FPGA IP 7.4.3. Ethernet Subsystem Intel FPGA IP
7.6. Transceiver Toolkit Scripts x
7.6.1. Supported Transceiver Toolkit Scripts 7.6.2. Modifying the Scripts 7.6.3. Script Execution 7.6.4. Example of the Results in Tcl Console
A. Appendix x
A.1. Agilex™ 7 F-Tile OPNs A.2. OSC_CLK_1 QSF Assignment Requirement A.3. FGT Internal Serial Loopback Calibration Sequence for RX Manual Adaptation
1. F-Tile Overview
2. F-Tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. F-Tile PMA/FEC Direct PHY Design Implementation
6. Supported Tools
7. Debugging F-Tile Transceiver Links
8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide
A. Appendix

3.6.4. FGT PMA Fractional Mode

Fo a give data ate, the dop-dow meu lists the suppoted itege mode efeece clock fequecies. Fo a give data ate, if the equied efeece clock fequecy is ot listed i the dop-dow, you ca eithe select oe of the suppoted itege mode efeece clock fequecies o eable factioal mode.

  • Whe eablig factioal mode, Altea ecommeds usig 141 MHz efeece clock fequecy to maximize the distace o the PLL spus acoss all OTN / SDI / CPRI ates.

  • VCO fequecy (MHz) = (M + k/2^22) * mul_div * efclk fequecy (MHz) / N

  • Output fequecy (MHz) = VCO fequecy (MHz) / L

    Whe the factioal PLL efeece clock fequecy is eteed, the IP GUI displays the VCO, M, N, L, k, ad mul_div values i the System Messages tab as show i the followig figue.

  • Fo a give data ate, you must eable factioal mode if you eed to dyamically cofigue the k coute duig u time.
Figue 83. Example of Factioal Settigs i System Messages Tab

FGT PMA suppots factioal mode i followig PMA modes:

Table 79.  FGT PMA Suppot fo Factioal Mode
PMA Mode Factioal Mode Suppot
TX simplex TX FGT PLL suppots factioal mode i TX simplex. To eable, select TX simplex optio fo PMA mode, ad tu o the Eable TX FGT PLL factioal mode i the paamete edito. The TX PLL factioal coute values automatically calculate fo the selected efeece clock fequecy. You ca place TX Simplex factioal mode o ay of 16 FGT TX PMAs.
Note: FGT PMA does ot suppot factioal mode fo RX simplex.
Duplex FGT PMA i Duplex PMA mode suppots factioal mode. To eable factioal mode i duplex PMA mode, select the Duplex optio fo PMA mode, select up to 16 fo the Numbe of PMA laes, ad tu o Eable TX FGT PLL factioal mode optio i the paamete edito.
  • I Duplex factioal mode, the output of each TX PLL is used as the efeece clock fo coespodig RX CDR. Each TX PLL is cofigued as factioal mode.
  • A sepaate efeece clock is ot equied fo RX CDR. TX PLL factioal coute values, ad RX CDR efeece clock fequecy, automatically calculate fo the selected efeece clock fequecy. You ca leave the x_cd_efclk_lik pot ucoected ad it is tied to goud iteally i the IP coe.
  • You ca place duplex factioal mode o ay of 16 FGT PMAs.
Pimay PLL cofiguatio To eable factioal mode with the pimay PLL cofiguatio, select the Duplex optio fo PMA mode, select 2 o 4 fo the Numbe of PMA laes, ad tu o Eable TX FGT PLL factioal mode ad Eable TX FGT PLL cascade mode optios i the paamete edito.
  • I Pimay PLL cofiguatio, the TX PLL of oe lae is i factioal mode ad acts as the efeece clock souce fo the local CDR ad TX PLL ad RX CDR blocks of othe laes (cofigued i itege mode) withi the quad.
  • Pimay PLL cofiguatio is ot suppoted whe you select 6 ,8, 12, o 16 fo the umbe of PMA laes.
  • You ca place the pimay PLL cofiguatio with 2 PMA laes eithe o FGT PMA Lae 1 ad 0 (same quad) of ay quad, with Lae 1 as the pimay. O FGT PMA Lae 3 ad 2 (same quad) of ay quad with lae 3 beig the pimay.
  • You ca place the pimay PLL cofiguatio with 4 PMA laes o FGT PMA Lae 3,2,1 ad 0 (same quad) of ay quad with Lae 3 beig the pimay.
  • Whe you place ay pimay PLL cofiguatio i Quad 2, you caot cofigue efeece clock [8] (accessible by Quad2) as output to povide RX ecoveed clock.
  • Whe you place ay pimay PLL cofiguatio i Quad 3, you caot cofigue efeece clock [9] (accessible by Quad3) as output to povide RX ecoveed clock.
Note: Refe to FGT PLL Cofiguatio i F-tile Achitectue Use Guide fo moe ifomatio.

Tuig the k Coute Value i Factioal Mode

Fo desigs with 1, 2, o 4 PMA laes, you ca cofigue the FGT PMA i factioal mode to adjust the fequecy ad dataate by a small amout fo ate matchig puposes.
  • Whe umbe of PMA laes is 1, tu o Eable TX FGT PLL factioal mode, set PMA efeece clock fequecy as 141 MHz, ad tue the k coute value of the lae.
  • Whe umbe of PMA laes is 2, o 4, tu o Eable TX FGT PLL factioal mode, tu o Eable TX FGT PLL cascade mode, set PMA efeece clock fequecy as 141 MHz, ad tue the k coute value of the pimay lae.
I ode to meet the jitte specificatios of OTN (Optical Taspot Netwok) ad SDI (Seial Digital Iteface), dyamic chages i the factioal value should have the followig limits:
  • Maximum step size: 2.5 ppm
  • Miimum duatio betwee steps: 1 us
If the OTN o SDI jitte specificatios does ot apply to you desig, ad you wat to adjust the data ate without losig lock, the dyamic chages i the factioal value should have the followig limits:
  • Maximum step size: 100 ppm
  • Miimum duatio betwee steps: ukow
Altea ecommeds keepig the duatio as log as you ca affod to get stable pefomace.

Each FGT PMA has a Avalo® memoy-mapped iteface egiste cotaiig the k coute. The k coute / 2^22 gives the factioal value K of the feedback coute. The factioal value K plus the M coute value povides the total feedback coute ad detemies how much PPM each bit i the k coute epesets. Fo example, the LSB (least sigificat bit) i the k coute epesets PPM = (1 / 2^22) / (K+M) × (10^6).

The pocedue to chage the k coute is:

  1. Chage the k coute to the ew value.
  2. Pulse the stobe bit 0 -> 1-> 0 to lock i the ew k coute.

Each FGT PMA cotais 3 PLLs; slow, medium ad fast. FGT PMAs ae ogaized i a quad. The k coute ad stobe bit Avalo® memoy-mapped iteface egiste addesses deped o the locatio of the tasceive i the quad ad which PLL is used (slow, medium, fast) as show i the table below.

Table 80.  FGT PMA Factioal k Coute ad Stobe Registe Addesses
Chael Locatio i Quad PLL Factioal k Coute Registe Stobe Registe
0 Slow 0x44000[30:9] 0x4400C[17]
Medium 0x44100[30:9] 0x4410C[17]
Fast 0x44200[30:9] 0x4420C[17]
1 Slow 0x4C000[30:9] 0x4C00C[17]
Medium 0x4C100[30:9] 0x4C10C[17]
Fast 0x4C200[30:9] 0x4C20C[17]
2 Slow 0x54000[30:9] 0x500C[17]
Medium 0x54100[30:9] 0x5410C[17]
Fast 0x54200[30:9] 0x5420C[17]
3 Slow 0x5C000[30:9] 0x5C00C[17]
Medium 0x5C100[30:9] 0x5C10C[17]
Fast 0x5C200[30:9] 0x5C20C[17]
You ca fid the tasceive locatio ad PLL selected i the <desig_ame>.sy.pt geeated by the Quatus® Pime Po Editio softwae as show i the followig figue.
Figue 84. Sample Quatus® Pime Po Editio Softwae Sythesis Compilatio Result 
; z1577a_u_ux_quad_3__ux3_syth_lc_med_e         ; eable                                   ; Stig        ;
; z1577a_u_ux_quad_3__ux3_syth_lc_med_f_out_hz           ; 0000000001010110011011010011111010000000 ; Usiged Biay;
; z1577a_u_ux_quad_3__ux3_syth_lc_med_f_pfd_hz           ; 0000000000000000000000000000000000000000 ; Usiged Biay;
; z1577a_u_ux_quad_3__ux3_syth_lc_med_f_ef_hz           ; 0000000000001000110110011110111000100000 ; Usiged Biay;
; z1577a_u_ux_quad_3__ux3_syth_lc_med_f_x_postdiv_hz    ; 0000000000010001010010010000110010000000 ; Usiged Biay;
; z1577a_u_ux_quad_3__ux3_syth_lc_med_f_tx_postdiv_hz    ; 0000000000000110111010100000010100000000 ; Usiged Biay;
; z1577a_u_ux_quad_3__ux3_syth_lc_med_f_vco_hz           ; 0000001010110011011010011111010000000000 ; Usiged Biay;
; z1577a_u_ux_quad_3__ux3_syth_lc_med_factioal_e      ; eable                                   ; Stig         ;
; z1577a_u_ux_quad_3__ux3_syth_lc_med_k_coute          ; 0000111010100111001110                   ; Usiged Biay;
; z1577a_u_ux_quad_3__ux3_syth_lc_med_l_coute          ; 001000                                   ; Usiged Biay;
; z1577a_u_ux_quad_3__ux3_syth_lc_med_m_coute          ; 000100111                                ; Usiged Biay;
; z1577a_u_ux_quad_3__ux3_syth_lc_med__coute          ; 000001                                   ; Usiged Biay;
; z1577a_u_ux_quad_3__ux3_syth_lc_med_powedow_mode     ; false                                    ; Stig         ;
; z1577a_u_ux_quad_3__ux3_syth_lc_med_pimay_use        ; ux3_syth_lc_med_pimay_use_disabled    ; Stig         ;
; z1577a_u_ux_quad_3__ux3_syth_lc_med_x_postdiv_coute ; 00101000                                 ; Usiged Biay;
; z1577a_u_ux_quad_3__ux3_syth_lc_med_tx_postdiv_coute ; 01100100                                 ; Usiged Biay;
; z1577a_u_ux_quad_3__ux3_syth_lc_med_tx_postdiv_factioal_e ; disable                            ; Stig         ;
I the sample compilatio esult show above, the FGT PMA is placed i quad 3, chael 3 ad the medium PLL is used. The M coute is 39 (000100111) ad the omial K value is 0.057 (0000111010100111001110/2^22). The LSB i the k coute epesets 6 ppb (pats pe billio) (1/2^22/39.057). The k coute egiste addess is 0x5C100[30:9] ad the stobe egiste bit addess is 0x5C10C[17].
Level Two Title