F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

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ID 683872
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile Overview 2. F-Tile Architecture 3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5. F-Tile PMA/FEC Direct PHY Design Implementation 6. Supported Tools 7. Debugging F-Tile Transceiver Links 8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives 9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide A. Appendix
1. F-Tile Overview x
1.1. Device Family Support
2. F-Tile Architecture x
2.1. F-Tile Building Blocks 2.2. F-Tile Placement Rules 2.3. PMA Architecture 2.4. Clock Architecture
2.1. F-Tile Building Blocks x
2.1.1. FHT and FGT PMAs 2.1.2. 400G Hard IP and 200G Hard IP 2.1.3. PMA Data Rates 2.1.4. FEC Architecture 2.1.5. PCIe* Hard IP 2.1.6. Bonding Architecture 2.1.7. Deskew Logic 2.1.8. Embedded Multi-die Interconnect Bridge (EMIB) 2.1.9. IEEE 1588 Precision Time Protocol for Ethernet 2.1.10. Clock Networks 2.1.11. Reconfiguration Interfaces
2.2. F-Tile Placement Rules x
2.2.1. PMA-to-Fracture Mapping 2.2.2. Determining Which PMA to Map to Which Fracture 2.2.3. Hard IP Placement Rules 2.2.4. IEEE 1588 Precision Time Protocol Placement Rules 2.2.5. Topologies 2.2.6. FEC Placement Rules 2.2.7. Clock Rules and Restrictions 2.2.8. Bonding Placement Rules 2.2.9. Preserving Unused PMA Lanes
2.2.1. PMA-to-Fracture Mapping x
2.2.1.1. FHT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.2. FGT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.3. FGT-PMA-to-200G-Hard-IP-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture x
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT 2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT 2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT 2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT 2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT 2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
2.2.5. Topologies x
2.2.5.1. Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) Example 2.2.5.2. Topology 6a: 400G Hard IP with Mixed Transceiver Mode Example 2.2.5.3. Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP Example
2.2.8. Bonding Placement Rules x
2.2.8.1. Bonded Lanes Use Case 1 2.2.8.2. Bonded Lanes Use Case 2
2.3. PMA Architecture x
2.3.1. FHT PMA Architecture 2.3.2. FGT PMA Architecture
2.3.1. FHT PMA Architecture x
2.3.1.1. FHT Transmitter PMA Architecture 2.3.1.2. FHT Receiver PMA Architecture 2.3.1.3. FHT PMA Loopback Modes
2.3.1.1. FHT Transmitter PMA Architecture x
2.3.1.1.1. FHT Transmitter Buffer and Phase Generator 2.3.1.1.2. FHT Serializer 2.3.1.1.3. FHT Gray-Coder and Pre-Coder 2.3.1.1.4. FHT Data Pattern Generator and Verifier
2.3.1.2. FHT Receiver PMA Architecture x
2.3.1.2.1. FHT Receiver Buffer and Equalizer 2.3.1.2.2. CDR Block 2.3.1.2.3. FHT Deserializer
2.3.2. FGT PMA Architecture x
2.3.2.1. FGT Transmitter PMA Architecture 2.3.2.2. FGT Receiver PMA Architecture 2.3.2.3. FGT PMA Tuning 2.3.2.4. FGT PMA Loopback Modes
2.3.2.1. FGT Transmitter PMA Architecture x
2.3.2.1.1. FGT Transmitter Buffer and Phase Generator 2.3.2.1.2. FGT Serializer 2.3.2.1.3. FGT Gray-Coder and Pre-Coder 2.3.2.1.4. FGT Data Pattern Generator and Verifier
2.3.2.2. FGT Receiver PMA Architecture x
2.3.2.2.1. FGT Receiver Buffer and Equalizer 2.3.2.2.2. Control Unit 2.3.2.2.3. FGT Deserializer
2.4. Clock Architecture x
2.4.1. Reference Clock Network 2.4.2. Datapath Clock Network 2.4.3. System PLL 2.4.4. Datapath Clock Cadences
2.4.1. Reference Clock Network x
2.4.1.1. FHT Reference Clock Network 2.4.1.2. FGT and System PLL Reference Clock Network 2.4.1.3. FGT Primary PLL Configuration
2.4.1.2. FGT and System PLL Reference Clock Network x
2.4.1.2.1. FGT Reference Clock Receiver Analog Front End
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview 3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.3. Configuring the IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting Reset 3.9. Bonding Implementation 3.10. Independent Port Configurations 3.11. Configuration Registers 3.12. Configurable Quartus® Prime Software Settings 3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. Unsupported PMA/FEC Modes
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.2.1. Preset IP Parameter Settings
3.3. Configuring the IP x
3.3.1. General and Common Datapath Options 3.3.2. TX Datapath Options 3.3.3. RX Datapath Options 3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options 3.3.5. Avalon® Memory Mapped Interface Options 3.3.6. Register Map IP-XACT Support 3.3.7. Example Design Generation 3.3.8. Analog Parameter Options
3.3.1. General and Common Datapath Options x
3.3.1.1. FGT PMA Configuration Rules for SATA mode 3.3.1.2. FGT PMA Configuration Rules for GPON Mode
3.3.2. TX Datapath Options x
3.3.2.1. TX PMA interface Parameters
3.3.3. RX Datapath Options x
3.3.3.1. RX FGT PMA Interface Options
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. RS-FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. TX PMA Control Signals 3.4.7. RX PMA Status Signals 3.4.8. TX and RX PMA and Core Interface FIFO Signals 3.4.9. PMA Avalon® Memory Mapped Interface Signals 3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals x
3.4.10.1. Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per Interface
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath x
3.5.1. Parallel Data Mapping Information 3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations 3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1) 3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2) 3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations x
3.5.2.1. TX Parallel Data Mapping Information for SATA Protocol Mode for Different Configurations
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. FGT PMA Fractional Mode 3.6.5. FGT RX CDR Clock Output
3.6.5. FGT RX CDR Clock Output x
3.6.5.1. Dynamically Configure the FGT RX CDR Clock Output
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the tx_cadence_slow_clk_locked Port 3.7.2. Rate Match FIFO
3.8. Asserting Reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Reset Signals—Descriptions 3.8.5. Status Signals—Descriptions 3.8.6. Run-time Reset Sequence—TX 3.8.7. Run-time Reset Sequence—RX 3.8.8. Run-time Reset Sequence—TX + RX 3.8.9. Run-time Reset Sequence—TX with FEC
3.8.8. Run-time Reset Sequence—TX + RX x
3.8.8.1. Run-time Reset Sequence Approximate Time Durations
3.11. Configuration Registers x
3.11.1. PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. FHT PMA Register Map 3.11.3. FGT PMA Register Map 3.11.4. FEC Register Map 3.11.5. Lane Offset Address 3.11.6. Accessing Configuration Registers
3.11.6. Accessing Configuration Registers x
3.11.6.1. Accessing PMA and FEC Direct PHY Soft CSR Registers 3.11.6.2. Accessing FHT PMA Registers 3.11.6.3. Accessing FGT PMA Registers
3.11.6.2. Accessing FHT PMA Registers x
3.11.6.2.1. FHT PMA Register Address Range 0x40000 to 0x48000 3.11.6.2.2. FHT PMA Register Address Range 0x60000 to 0xF0030 3.11.6.2.3. FHT PMA Register Address 0xFFFFC
3.11.6.3. Accessing FGT PMA Registers x
3.11.6.3.1. FGT PMA Register Address Range 0x40000 to 0x48000 3.11.6.3.2. FGT PMA Register Address Range 0x62000 to 0x62004 3.11.6.3.3. FGT PMA Register Address Range 0x9003C to 0xF0028 3.11.6.3.4. FGT PMA Register Address 0xFFFFC
3.12. Configurable Quartus® Prime Software Settings x
3.12.1. FHT PMA Settings 3.12.2. FGT PMA Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing x
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.13.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP x
3.13.2.1. RTL Connection Example for JTAG to Avalon® Master Bridge Intel IP
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. FHT PMA 3.14.2. FGT PMA
3.14.1. FHT PMA x
3.14.1.1. Enabling Loopback 3.14.1.2. Enabling the PRBS Generator and Verifier for ES Devices 3.14.1.3. Obtaining BER Values for Production Devices 3.14.1.4. TX Equalizer Settings 3.14.1.5. TX Error Injection 3.14.1.6. RX Reconvergence 3.14.1.7. Preserving Unused Lanes
3.14.2. FGT PMA x
3.14.2.1. Direct Register Method 3.14.2.2. FGT Attribute Access Method
3.14.2.1. Direct Register Method x
3.14.2.1.1. Direct Register Method Examples
3.14.2.2. FGT Attribute Access Method x
3.14.2.2.1. FGT Attribute Access Method Example 1 3.14.2.2.2. FGT Attribute Access Method Example 2 3.14.2.2.3. FGT Attribute Access Method Example 3
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for F-Tile Reference and System PLL Clocks Intel® FPGA IP Usage 4.5. Guidelines for Refclk #i is Active At and After Device Configuration 4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs
4.5. Guidelines for Refclk #i is Active At and After Device Configuration x
4.5.1. Guidelines for System PLL Reference Clock 4.5.2. Guidelines for FGT Reference Clock
4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs x
4.6.1. How to Read the Real-Time Lock Status of the FGT TX PLL 4.6.2. How to Read the Real-Time Lock Status of the FHT Lane TX PLL 4.6.3. How to Read the Real-Time Lock Status of the FHT Common TX PLL 4.6.4. How to Reset the FGT TX PLL 4.6.5. How to Reset the FHT Lane TX PLL and Common PLL
4.6.1. How to Read the Real-Time Lock Status of the FGT TX PLL x
4.6.1.1. How to Determine the TX PLL Your FGT Channel is Using
4.6.3. How to Read the Real-Time Lock Status of the FHT Common TX PLL x
4.6.3.1. How to Determine Which Common PLL Your FHT Channel is Using
5. F-Tile PMA/FEC Direct PHY Design Implementation x
5.1. Implementing the F-Tile PMA/FEC Direct PHY Design 5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5.5. Enabling Custom Cadence Generation Ports and Logic 5.6. Connecting the F-Tile PMA/FEC Direct PHY Design IP 5.7. Simulating the F-Tile PMA/FEC Direct PHY Design 5.8. F-Tile Interface Planning
5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
5.2.1. Setting General and Common Datapath Options 5.2.2. Setting TX Datapath Options 5.2.3. Setting RX Datapath Options
5.7. Simulating the F-Tile PMA/FEC Direct PHY Design x
5.7.1. PAM4 Encoding Schemes in Simulation
5.8. F-Tile Interface Planning x
5.8.1. F-Tile Interface Planner Usage Example
6. Supported Tools x
6.1. F-Tile Channel Placement Tool 6.2. F-Tile PMA and FEC Direct Port Mapping Calculator 6.3. F-Tile Clocking and Datapath Tool 6.4. F-Tile FGT TX Equalizer Tool
7. Debugging F-Tile Transceiver Links x
7.1. F-Tile Transceiver Toolkit GUI 7.2. F-Tile Transceiver Debugging Flow Walkthrough 7.3. Transceiver Toolkit Parameter Settings 7.4. Using F-Tile Multirate IPs with Transceiver Toolkit 7.5. Troubleshooting Common Errors 7.6. Transceiver Toolkit Scripts
7.1. F-Tile Transceiver Toolkit GUI x
7.1.1. Collection View
7.2. F-Tile Transceiver Debugging Flow Walkthrough x
7.2.1. Modifying the Design to Enable F-Tile Transceiver Debug 7.2.2. Programming the Design into an Intel FPGA 7.2.3. Loading the Design to the Transceiver Toolkit 7.2.4. Creating Transceiver Links 7.2.5. Running BER Tests 7.2.6. Running Eye Viewer Tests 7.2.7. Running Link Optimization Tests 7.2.8. Checking FEC Statistics 7.2.9. Vertical Bathtub Curve Measurements (VBCM) Data
7.3. Transceiver Toolkit Parameter Settings x
7.3.1. Dashboard
7.4. Using F-Tile Multirate IPs with Transceiver Toolkit x
7.4.1. F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP 7.4.2. F-Tile Ethernet Multirate Intel FPGA IP 7.4.3. Ethernet Subsystem Intel FPGA IP
7.6. Transceiver Toolkit Scripts x
7.6.1. Supported Transceiver Toolkit Scripts 7.6.2. Modifying the Scripts 7.6.3. Script Execution 7.6.4. Example of the Results in Tcl Console
A. Appendix x
A.1. Agilex™ 7 F-Tile OPNs A.2. OSC_CLK_1 QSF Assignment Requirement A.3. FGT Internal Serial Loopback Calibration Sequence for RX Manual Adaptation
1. F-Tile Overview
2. F-Tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. F-Tile PMA/FEC Direct PHY Design Implementation
6. Supported Tools
7. Debugging F-Tile Transceiver Links
8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide
A. Appendix

9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

Document Version Quartus® Prime Version Changes
2024.11.04 24.3 Made the following changes:
  • Updated the compliance specifications in the F-Tile Supported FEC Modes and Compliance Specifications table in the FEC Architecture section.
  • Added topology 16 in the F-Tile Topologies table in the Topologies section.
  • Removed the reverse parallel loopback option from the FHT PMA Loopback Modes section.
  • Updated the FGT Gray-Coder and Pre-Coder section with PAM4 information.
  • Updated the FGT Receiver Buffer and Equalizer section with information about the cut-off frequency.
  • Corrected a typo in the first equation of transmitter buffer equalizer parameter combinations for the production devices in the FGT Transmitter Buffer and Phase Generator section.
  • Updated the PMA Direct Supported Mode table for the NRZ modulation FGT PMA in PMA clocking mode with 16 bit PMA interface width support.
  • Updated the FGT PMA Configuration Rules for GPON Mode section with additional information about burst mode and guidelines to utilize the LTR mode.
  • Updated the Enable Gray coding parameter description in the RX FGT PMA Parameters table.
  • Updated the Enable fgt_rx_cdr_set_locktoref port parameter description in the RX FGT PMA Parameters table.
  • Updated the Enable fgt_rx_set_locktoref port and Enable fgt_rx_set_locktodata port parameter descriptions in the RX FGT PMA Parameters table.
  • Updated the tx_pll_locked signal description in the TX and RX Reference Clock and Clock Output Interface Signals and Status Signals—Descriptions sections.
  • Updated the tx_pll_locked signal description in the Runtime-Reset-Sequence-TX and Run-time Reset Sequence—TX + RX sections.
  • Added TX PLL Bandwidth instance assignment settings in the FGT PMA Settings section.
  • Removed reverse parallel loopback setting for FHT PMA from the Loopback Mode Register Settings table.
  • Added new topic Obtaining BER Values for Production Devices for FHT PMA in the Hardware Configuration Using the Avalon® Memory-Mapped Interface section.
  • Updated the en_refclk_fgt_i, refclk_fgt_enabled_i, and refclock_status signal descriptions in the F-Tile Reference and System PLL Clocks Intel® FPGA IP Port List table.
  • Updated the Guidelines for F-Tile Reference and System PLL Clocks Intel® FPGA IP Usage with requirement to have only one F-Tile Reference and System PLL Clocks Intel® FPGA IP per F-Tile.
  • Updated the Guidelines for System PLL Reference Clock section with information about the input signal en_refclk_fgt_i requirements.
  • Updated the Guidelines for FGT Reference Clock section with information about the input signal en_refclk_fgt_i transition requirements.
  • Added new section Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs in the Implementing the F-Tile Reference and System PLL Clocks Intel FPGA IP chapter.
  • Updated the Simulating the F-Tile PMA/FEC Direct PHY Design section with additional information about the simulation setup and files.
  • Updated the Troubleshooting Common Errors section with information about troubleshooting the TX PMA Reference Clock.
  • Updated Agilex 7 FPGAs and SoCs Ordering Part Number figure in Appendix A.1. Agilex 7 F-Tile OPNs.
  • Added Appendix A.3. FGT Internal Serial Loopback Calibration Sequence for RX Manual Adaptation.
2024.07.08 24.2 Made the following changes:
  • Added top-level block diagram in the F-Tile Building Blocks section.
  • Updated the interface type support for the 2x PCIe x4 and 1x PCIe x4 in the PCIe Hard IP (Gen4, Gen3, Gen2, and Gen1) Supported Configurations table.
  • Updated the Clock Rules and Restrictions section with information about having a stable and running reference clock for the FGT PMA.
  • Updated the Preserving Unused PMA Lanes section with information about asserting the PHY reset for unused PMAs.
  • Updated the PMA Direct Mode Support table with a few PMA widths that are not supported.
  • Updated the FEC Direct Mode Support table with a few PMA widths that are not supported.
  • Updated the General and Common Datapath Options table with a new parameter Enable per PMA lanes TX and RX ready signal.
  • Updated the RS-FEC (Reed Solomon Forward Error Correction) Options section with information about accessing the CWBIN0-3 registers.
  • Updated the default value of the Enable FGT VSR mode parameter in the FGT RX Analog Parameter Options table.
  • Updated the TX and RX Reference Clock and Clock Output Interface Signals table about the tx_pll_refclk_link[N-1:0] and rx_cdr_refclk_link[N-1:0] signal connections.
  • Updated the Accessing Configuration Registers section extensively and added new information and sub-sections.
  • Updated the VSR mode settings in the FGT PMA Settings topic in the Configurable Quartus Prime Software Settings section.
  • Updated the Reverse Parallel Loopback steps in the Direct Register Method Examples topic with the reset and FEC requirements.
  • Added VSR mode settings in the FGT Attribute Access Data Value 3 table in the FGT Attribute Access Method section.
  • Updated the F-Tile Reference and System PLL Clocks Intel FPGA IP Port List table with additional description and recommendation for the disable_refclk_monitor_i signal and a note for the avmm_clk, avmm_reset, and out_coreclk_i signals.
  • Updated the Guidelines for F-Tile Reference and System PLL Clocks Intel FPGA IP Usage section with information about system PLL usage for PCIe* and other protocols together.
  • Updated the Guidelines for Refclk #i is Active At and After Device Configuration section.
  • Updated the Guidelines for FGT Reference Clock section with additional information about the Refclk #i monitor setting.
2024.04.01 24.1 Made the following changes:
  • Added new topic Device Family Support in F-Tile Overview section with Agilex™ 9 support.
  • Added new topic FGT PMA Configuration Rules for GPON Mode in General and Common Datapath Options section.
  • Updated formula for VCO Frequency in FGT PMA Fractional Mode section.
  • Updated Dynamically Configure the FGT RX CDR Clock Output section with RX reset ACK requirement step.
  • Added Hardware Max time column in Run-time Reset Sequence Approximate Time Durations table.
  • Corrected PMA lanes to 8 from 10 in Accessing FGT PMA Registers section examples.
  • Updated FGT PMA Settings section with RX invert P and N and TX invert P and N .qsf settings.
  • Added footnote to TX to RX Parallel Loopback in Direct Register Method Examples topic.
  • Updated the steps in Measuring the Bit Error Rate (BER) with FGT PMAs in Direct Register Method Examples topic.
  • Updated the FGT Attribute Access Data Value 1 table in the FGT Attribute Access Method section.
  • Updated FGT Attribute Access Method Example 1 and FGT Attribute Access Method Example 2 sections with RX reset ACK requirement step.
  • Added note to Port Connection Guidelines between F-Tile Reference and System PLL Clocks Intel® FPGA IP and F-Tile PMA/FEC Direct PHY Intel® FPGA IP table about no simulation support.
  • Added information about how to set the Refclk #i is active at and after device configuration parameter at device power-up if a stable Refclk #i is not present in the Guidelines for Refclk #i is Active At and After Device Configuration section.
  • Updated the Simulating the F-Tile PMA/FEC Direct PHY Design section with information about the top level entity instantiation.
  • Added new topic Dashboard in the Debugging F-Tile Transceiver Links section with information about the dashboard feature.
  • Added new topic Using the Multirate IPs with Transceiver Toolkit in the Debugging F-Tile Transceiver Links section with information about using the transceiver toolkit with the F-Tile Multirate IPs.
  • Updated A.1 F-Tile Production Revision OPNs in Appendix with information about production OPNs.
2024.01.24 23.4 Made the following changes:
  • Updated the TX FHT PMA Parameters in Parameter Editor figure and TX FHT PMA Parameters table in the TX Datapath Options section.
  • Updated the RX FHT PMA Parameters in Parameter Editor figure and RX FHT PMA Parameters table in the RX Datapath Options section.
  • Updated description of the Export Refclk #0-9 for use in user logic parameters in the F-Tile Reference and System PLL Clocks Intel® FPGA IP Parameters table.
  • Updated description of the out_coreclk_i port in the F-Tile Reference and System PLL Clocks Intel® FPGA IP Port List table.
2023.12.04 23.4 Made the following changes:
  • Added note in F-Tile Building Blocks section about 200G hard IP support in Agilex™ 7 device OPNs.
  • Updated NRZ and PAM4 support information for Quad0 in the Hard IP Placement Rules section.
  • Updated the first and second bullet in Clock Rules and Restrictions section with additional information.
  • Updated the FHT PMA Analog Parameter figure and the FHT RX Analog Parameter table in the Analog Parameter Options section.
  • Removed hardware max time information in the Run-time Reset Sequence Approximate Time Durations table.
  • Removed PRBS 11 selection value and added PRBS 15 selection value in the FGT Attribute Access Data Value 1 table.
  • Updated the F-Tile Reference and System PLL Clocks Intel FPGA IP Port List table with new ports and reordered the port list.
  • Added new topic Guidelines for FGT Reference Clock in the Guidelines for Refclk #i is Active At and After Device Configuration section.
  • Added note in F-Tile Channel Placement Tool section about 200G hard IP support in Agilex™ 7 device OPNs.
  • Added information about gray code setting for FHT PMA in Running BER Tests topic.
  • Added new topic Vertical Bathtub Curve Measurements Data about exporting the VBCM data.
  • Added new parameters to the Transceiver Toolkit Parameter Settings table.
  • Updated the paths in the Transceiver Toolkit Script Location table.
  • Added Appendix A.2 about the new OSC_CLK_1 .qsf assignment requirement.
2023.10.02 23.3 Made the following changes:
  • Updated bullet related to 400G hard IP support in Hard IP Placement Rules section.
  • Corrected Number of PMAs to 12 for 400G Hard IP for topology 14 in the F-Tile Topologies table.
  • Corrected registers to resistors in note in FGT Reference Clock Receiver Analog Front End section.
  • Removed support for USB protocol mode in several topics.
  • Added new parameters Adaptation mode and Enable fgt_rx_set_locktodata port in the RX FGT PMA Parameters table.
  • Updated the values equation for Selected rx_cdr_divclk_link0 source parameter in the RX FGT PMA Parameters table.
  • Updated default setting to Enabled for Enable FHT RX data profile parameter in the RX FHT PMA Parameters table.
  • Removed references to port rx_cdr_divclk_link1 in TX and RX Reference Clock and Clock Output Interface Signals table.
  • Added new signal fgt_rx_set_locktodata[N-1:0] to the RX PMA Status Signals table.
  • Removed port rx_cdr_divclk_link1 from Signal and Port Reference topic.
  • Updated Clock ports section with a note about tx_clkout and tx_clkout2 clock, and rx_clkout and rx_clkout2 clocks being asynchronous to each other.
  • Added new topic Analog Parameter Options about the Analog Parameters tab in Configuring the IP section.
  • Added new topics FGT RX CDR Clock Output and Dynamically Configure the FGT RX CDR Clock Output in the Clocking section.
  • Updated the Independent Port Configurations section with additional information.
  • Updated the Accessing FGT PMA Registers section with additional information for FGT PMA registers with offset address as 0x62000, 0x62004, or 0x62008.
  • Corrected the TX invert P and N setting in the FHT PMA Settings section.
  • Updated the Configuring the F-Tile PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing section with additional information.
  • Added new table FGT Attribute Access Data Value 3 with opcode for RX CDR clock in FGT Attribute Access Method section.
  • Added additional description for Refclk frequency #N parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP Parameters table.
  • Removed ports en_refclk_fgt_i[1:0] and refclk_fgt_enabled_i from the F-Tile Reference and System PLL Clocks Intel FPGA IP Port List table.
  • Added port refclock_status to the F-Tile Reference and System PLL Clocks Intel FPGA IP Port List table.
  • Removed section Guidelines for FGT Reference Clock in the Implementing the F-Tile Reference and System PLL Clocks Intel FPGA IP chapter.
  • Added additional information about VHDL simulation in step 7. of Simulating the F-Tile PMA/FEC Direct PHY Design section.
  • Added new topic Checking FEC Statistics in the F-Tile Transceiver Debugging Flow Walkthrough section.
  • Removed two M-Series ES devices from the OPN list in Appendix A.1.
2023.06.26 23.2 Made the following changes:
  • Removed redundant figure from FGT-PMA-to-400G-Hard-IP-Fracture Mapping section.
  • Removed the list of OPNs and updated FGT Transmitter Buffer and Phase Generator section with OPN list link in Appendix A.1.
  • Added new section FGT Reference Clock Receiver Analog Front End describing termination requirements for the FGT reference clock.
  • Updated description for the Enable fgt_rx_cdr_fast_freeze_sel port and Enable fgt_rx_cdr_freeze port parameters in the RX FGT PMA Parameters table.
  • Added note about how to access the CWBIN and FEC registers in the RS-FEC (Reed Solomon Forward Error Correction) Options section.
  • Added note in description column of TX and RX Reference Clock and Clock Output Interface Signals table for rx_clkout, rx_clkout2, tx_clkout, tx_clkout2 signals.
  • Updated description for fgt_rx_cdr_freeze[N-1: 0] signal and added new signal fgt_rx_cdr_fast_freeze_sel[N-1: 0] in RX PMA Status Signals table.
  • Added frequency range for reconfig_xcvr_clk and reconfig_xcvr<n>_clk clock signals in PMA Avalon® Memory Mapped Interface Signals section.
  • Added frequency range for reconfig_pdp_clk and reconfig_pdp<n>_clk clock signals in Datapath Avalon® Memory Mapped Interface Signals section.
  • Removed the FGT Core PLL Mode section as the mode is no longer supported in the Quartus® Prime Pro Edition software.
  • Reorganized the content in the Configurable Quartus® Prime Software Settings section.
  • Updated the FGT PMA Settings section with valid parameter settings for TX Equalization and RX Manual Equalization parameters.
  • Updated the Direct Register Method Examples section with Measuring the Bit Error Rate (BER) with FGT PMAs example and a note for Internal Serial Loopback and Polarity Inversion examples.
  • Updated the FGT Attribute Access Data Value 2 table with Get Status opcodes.
  • Removed parameter Refclk is available at device configuration from the F-Tile Reference and System PLL Clocks Intel® FPGA IP Parameters table.
  • Updated the F-Tile Reference and System PLL Clocks Intel® FPGA IP Parameters table with new parameters Refclk #n is active at and after device configuration and Export Refclk #n for use in user logic
  • Updated the F-Tile Reference and System PLL Clocks Intel® FPGA IP Port List table with the following signals; avmm_clk, avmm_reset, refclock_ready [2:0], en_refclk_fgt_i[1:0], refclk_fgt_enabled_i, and out_coreclk_i.
  • Replaced section Guidelines to Indicate all System PLL Reference Clocks are Ready with new section Guidelines for Refclk #i is Active At and After Device Configuration.
  • Replaced section Example of Reference Clock Availability at Device Programming with new section Guidelines for System PLL Reference Clock.
  • Replaced section Example Flow to Indicate All System PLL Reference Clocks are Ready with new section Guidelines for FGT Reference Clock.
  • Removed the chapter Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP from the user guide as the IP is no longer supported in the Quartus® Prime Pro Edition software.
  • Removed the list of OPNs and updated F-Tile TX Equalizer Tool section with OPN list link in Appendix A.1.
  • Updated the Tcl File Name and Path of scripts in the Supported Transceiver Toolkit Scripts section.
  • Added Appendix A.1 with list of F-tile Production Revision and Firmware OPNs.
2023.04.03 23.1 Made the following changes:
  • Updated the product family name to Intel Agilex 7.
  • Added new information about mixed transceiver mode (topology 6a) support in 400G Hard IP and 200G Hard IP, PMA-to-Fracture Mapping, and Topologies sections.
  • Updated Fracture Type Used by Mode table with 200GbE-4 support in st_x16 row.
  • Updated Clock Rules and Restrictions section with additional requirements for a stable reference clock.
  • Updated FGT Transmitter PMA Equalizer Parameters for NRZ and PAM4 Modes tables with additional information and missing default values.
  • Updated FGT Data Pattern Generator and Verifier section with PRBS and SSPR specification information.
  • Updated FGT PMA Loopback Modes section with additional information about the various loopback modes.
  • Updated FGT PMA Loopback Modes figure with missing connection.
  • Added description about the 32-bit soft CWBIN counters in RS-FEC (Reed Solomon Forward Error Correction) Options section.
  • Added new parameters Include 32bit soft CWBIN counters and Reconfig clock frequency in RS-FEC Parameters table for soft CWBIN counters support.
  • Updated FGT PMA Fractional Mode section with corrected information about setting the fractional mode.
  • Added new section Accessing Configuration Registers with detailed information about how to use the offset address in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP register map to access the registers.
  • Corrected Configurable Quartus® Prime Software Settings section with FGT TX equalization example qsf values for txeq_pre_tap_1 and txeq_post_tap_1 and added a note in the section.
  • Updated the bypass RX auto adaptation qsf assignments and added the RX manual equalization qsf assignments in Configurable Quartus® Prime Software Settings section.
  • Corrected Direct Register Method Example section with TX equalizer pre-cursor 1 register and TX equalizer post-cursor 1 register addresses for FGT PMA.
  • Added additional FGT PMA setting examples in Direct Register Method Examples section.
  • Added note in FGT Attribute Access Method Example 2 section about register 0x90040[25:24] status values.
  • Updated F-Tile Reference and System PLL Clocks Intel® FPGA IP Parameters table with renamed Refclk is available at device configuration parameter.
  • Updated Example Flow to Indicate All System PLL Reference Clocks are Ready section with Refclk is available at device configuration parameter renaming.
  • Added Enable Debug Master Endpoint on Global AVMM parameter to the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP Parameters table.
  • Updated Hardware Flow Using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP section with usage information about Enable Debug Master Endpoint on Global AVMM parameter.
  • Added note in Running Eye Viewer Tests section about no support for 2D Eye plots.
  • Added new section Transceiver Toolkit Scripts with information about using scripts available in the Quartus® Prime Pro Edition software version 23.1 for transceiver testing.
2023.01.25 22.4 Updated the FHT Loopback Mode figure with the correct Deserializer block location.
2022.12.19 22.4 Made the following changes:
  • Updated Clock Rules and Restrictions section with additional information about the reference clocks and a new note.
  • Updated FGT Transmitter PMA Equalizer Parameters for NRZ and PAM4 Modes table; renamed cursor to tap, and updated the footnotes.
  • Added equations based on device OPN list for the transmitter buffer equalizer parameters in the FGT Transmitter Buffer and Phase Generator section.
  • Corrected the preset naming in the F-Tile PMA/FEC Direct PHY Intel FPGA IP Available Parameter Presets table in Preset IP Parameter Settings section.
  • Updated the description for the PMA parallel clock frequency parameter in General and Common Datapath Options table.
  • Updated the Show Preset Settings figure in Example Design Generation section.
  • Corrected tx_coreclkin and rx_coreclkin signal names in Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source section.
  • Corrected the k counter descriptions and equations in FGT PMA Fractional Mode section.
  • Added new information about meeting jitter specifications for OTN/SDI and in other modes in FGT PMA Fractional Mode section.
  • Updated rx_ready signal description in Reset Signal Descriptions table.
  • Updated the steps and figure in the Run-time Reset Sequence—TX section.
  • Updated the steps and figure in the Run-time Reset Sequence—RX section.
  • Updated the steps and figure in the Run-time Reset Sequence—TX + RX section.
  • Updated column header for FHT PMA Lane Number and Offset Address and FGT PMA Lane Number and Offset Address tables in Lane Offset Address section.
  • Updated descriptions for calculating the incremental lane numbers for the FHT PMA and FGT PMA in Lane Offset Address section.
  • Added .qsf settings to bypass RX auto adaptation in Configurable Intel Quartus Prime Software Settings section.
  • Updated Guidelines for F-Tile Reference and System PLL Clocks Intel FPGA IP Usage with additional information about the system PLL reference clock.
  • Updated Guidelines to Indicate all System PLL Reference Clocks are Ready with additional information about using the internal clock to calibrate and configure the device, information about PCIe specification compliance, and OPN device list that supports Refclk is available at power-on parameter.
  • Added additional information in Example of Reference Clock Availability at Device Programming section to clarify the example.
  • Added tip for step 5b. in Hardware Flow Using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP .
  • Added new section Examples of Register Access Using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP with several topics with examples.
  • Updated the FGT transmitter equalizer cursor naming, added additional tool link for various devices based on OPNs, and updated figure in F-Tile TX Equalizer Tool section.
  • Updated the FGT transmitter equalizer cursor naming, updated descriptions for RX Ready and PRBS locked parameters in Transceiver Toolkit Parameter Settings table.
2022.11.03 22.3 Added a clarifying note about the SATA and USB protocol modes in sections: FGT PMA Configuration Rules for SATA and USB mode and TX Parallel Data Mapping Information for SATA and USB Protocol Modes for Different Configurations.
2022.09.26 22.3 Made the following changes:
  • Updated FGT Transmitter PMA Equalizer Parameters for NRZ and PAM4 Modes table with total slice values for different OPNs.
  • Updated tx_reset_ack and rx_reset_ack signal descriptions in the Reset Signals and Reset Signal Descriptions tables.
  • Added new parameters FGT PMA configuration rules and Enable simplified TX data interface in General and Common Datapath Options table.
  • Added new section FGT PMA Configuration Rules for SATA and USB mode.
  • Added new parameters Enable fgt_tx_beacon port and Enable Spread Spectrum clocking in TX FGT Datapath Parameters table for SATA and USB support.
  • Added new parameters Enable fgt_rx_cdr_fast_freeze_sel port and Enable fgt_rx_cdr_set_locktoref port in RX FGT PMA Parameters table for GPON support.
  • Updated descriptions for Enable fgt_rx_signal_detect port and Enable fgt_rx_signal_detect_lfps port parameters in RX FGT PMA Parameters table for SATA and USB support.
  • Corrected TX PMA Status Signals to TX PMA Control Signals and added new signal fgt_tx_pma_elecidle to the table.
  • Added new section TX Parallel Data Mapping Information for SATA and USB Protocol Modes for Different Configurations.
  • Updated and replaced PMA Avalon® memory-mapped with Global Avalon® memory-mapped interface in Guidelines to Indicate all System PLL Reference Clocks are Ready section and the examples.
  • Added additional examples in step 6. of Hardware Flow Using the F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP section.
  • Updated Simulating the F-Tile PMA/FEC Direct PHY Design section with information about the auto-generated file names.
2022.06.24 22.2 Made the following changes:
  • Updated F-Tile Supported FEC Modes and Compliance Specifications table with Fibre Channel 64G support and added note.
  • Clarified fourth bullet in Clock Rules and Restrictions section with updated rules for the FHT microcontroller reference clock.
  • Added new figure for TX termination in FGT Transmitter Buffer and Phase Generator.
  • Added new figure for RX termination in FGT Receiver Buffer and Equalizer.
  • Added new topic Register Map IP-XACT Support in Configuring the IP section.
  • Added instructions to simulate example design using VCS* MX and Xcelium* simulators in Example Design Simulation section.
  • Added note for tx_pll_refclk_link and rx_cdr_refclk_link signals in the TX and RX Reference Clock and Clock Output Interface Signals table.
  • Updated FGT Attribute Access Method section with additional information and tables.
  • Added a new example for serial loopback enable and disable in FGT Attribute Access Method section.
  • Deleted note in step 7. of FGT Attribute Access Method Example 2.
  • Added new parameter Refclk is available at power-on in Implementing the F-Tile Reference and System PLL Clocks Intel FPGA IP chapter.
  • Added new section Guidelines to Indicate all System PLL Reference Clocks are Ready in Implementing the F-Tile Reference and System PLL Clocks Intel FPGA IP chapter.
  • Updated step 5. of Hardware Flow Using the F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP.
  • Added FEC alignment marker information and table in Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel FPGA IP
  • Added data scrambling and de-scrambling information for FEC in Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel FPGA IP.
  • Updated Running Eye Viewer Tests with an additional step and figures.
  • Added information about Autosweep in Running Link Optimization Tests.
2022.03.28 22.1 Made the following changes:
  • Clarified third bullet in Clock Rules and Restrictions section with updated rules for the system PLL reference clock.
  • Added note about bonding rules in the Bonding Placement Rules section.
  • Added new topic Tuning the Fractional Value in Fractional Mode in the FGT PMA Fractional Mode section.
  • Added PMA Reconfiguration Interface column in the Reset Signals—Block Level table and added a note about the reconfig_xcvr_reset signal usage.
  • Updated TX equalization main tap example setting for FHT PMA in Configurable Intel Quartus Prime Software Settings section.
  • Added FGT Attribute Access Method Example 2 in FGT Attribute Access Method section for TX and RX polarity inversion.
  • Updated Running BER Tests section with information about the Actions sub-menu.
  • Updated Running Eye Viewer Tests section with detailed description about using the Eye Viewer tool for eye height measurement for the FGT PMA.
2021.12.15 21.4 Made the following changes:
  • Updated Increment and Decrement Size column in the FGT Transmitter PMA Equalizer Parameters for NRZ and PAM4 Modes table.
  • Added footnote for System PLL frequency description in General and Common Datapath Options table.
  • Added footnote for TX FGT PLL reference clock frequency description in TX FGT Datapath Parameters table.
  • Added footnote to TX and RX Reference Clock and Clock Output Interface Signals table.
  • Removed note for Enable rx_cdr_divclk_link0 port and Enable rx_cdr_divclk_link1 port parameters in the RX FGT PMA Parameters table.
  • Updated Example Design Generation with RS-FEC example design information.
  • Added note to Clocking section in Implementing the F-Tile PMA/FEC Direct PHY Intel FPGA IP chapter.
  • Added RX invert P and N, RX termination, TX invert P and N, TX termination, TX out tristate enable and TX equalization qsf settings for FHT PMA in Configurable Intel Quartus Prime Software Settings section.
  • Removed RX termination mode select qsf setting for FGT PMA in Configurable Intel Quartus Prime Software Settings section.
  • Added TX equalization qsf setting for FGT PMA in Configurable Intel Quartus Prime Software Settings section.
  • Updated steps 4a, 6, 8a, 10c, 13c, 14b and 14c in the FGT Attribute Access Method Example topic.
  • Reorganized information in the Implementing the F-Tile Reference and System PLL Clocks Intel FPGA IP chapter to make it clearer.
  • Removed note for Enable FGT CDR Output #0 and Enable FGT CDR Output #1 parameters in the F-Tile Reference and System PLL Clocks Intel FPGA IP Parameters table.
  • Added description to specify qsf location assignment for the out_cdrclk_i port in the F-Tile Reference and System PLL Clocks Intel FPGA IP Port List table.
  • Added new section Guidelines for F-Tile Reference and System PLL Clocks Intel FPGA IP Usage.
  • Updated step 5 of the Hardware Flow Using the F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP section.
  • Updated F-tile PMA/FEC Direct PHY Design Implementation chapter to remove references to design example.
  • Updated F-Tile Transceiver Toolkit GUI, Collection View Tab of the F-Tile Transceiver Toolkit GUI, Toolkit Explorer, Example BER Test Setup and Results for the FGT PMA figures in the Debugging F-Tile Transceiver Links chapter.
  • Updated PMA naming in the Running BER Tests section.
  • Updated Transceiver Toolkit Parameter Settings table with new information.
  • Updated Creating Transceiver Links section with Import Collections and Export Collections details.
  • Added footnote for TX Equalization Parameters in the Transceiver Toolkit Parameter Settings table.
2021.10.15 21.3 Made the following changes:
  • Updated the Preserving Unused PMA Lanes section.
  • Updated the Number of system copies parameter in General and Common Datapath Options table.
  • Added Enable Core PLL mode parameter in TX FGT Datapath table.
  • Updated Enable FHT RX data profile parameter in RX FHT PMA Parameters table.
  • Updated the Example Design Generation topic in the Configuring the IP section.
  • Updated parameter names to match with GUI names in Avalon® Memory Mapped Interface Parameters table.
  • Added description for Number of system copies parameter in the Signal and Port Reference section.
  • Updated description of the FGT PMA Fractional Mode section.
  • Added new topic Run-time Reset Sequence Approximate Time Duration in Run-time Reset Sequence—TX + RX section.
  • Updated step 4 onwards in the Run-time Reset Sequence—TX with FEC section
  • Updated description of the Lane Offset Address section.
  • Added new topic Logical Avalon Memory-Mapped Port Indexing in Configuration Registers section.
  • Updated steps in FGT Attribute Access Method Example.
  • Added footnote that ETHERNET_FREQ_805_322 is not supported in section Mode of System PLL - System PLL Reference Clock and Output Frequencies.
  • Added new section Hardware Flow Using the F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP in Implementing the F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP chapter.
  • Added the following new sections in the F-tile PMA/FEC Direct PHY Design Example Implementation chapter.
    • Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel FPGA IP.
    • PAM4 Encoding Schemes in Simulation.
    • F-tile Interface Planner Design Example.
    • Updated the Simulating the F-tile PMA/FEC Direct PHY Design Example section.
  • Added and updated the following sections in the Supported Tools chapter.
    • F-Tile PMA and FEC Direct Port Mapping Calculator.
    • F-Tile Clocking and Datapath Tool.
    • F-Tile TX Equalizer Tool.
  • Added new chapter Debugging F-Tile Transceiver Links.
2021.08.18 21.2
  • Added the following new sections and updated table in Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP chapter:
    • Configuration Registers.
    • Configurable Quartus® Prime Software Settings.
    • Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing.
    • Hardware Configuration Using the Avalon® Memory-Mapped Interface.
    • Added loopback mode in TX FHT PMA Parameters table.
  • Added new topic in F-Tile Placement Rules section in the F-Tile Architecture chapter:
    • Preserving Unused PMA Lanes.
  • Added new chapter Supported Tools.
  • Added new chapter Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide.
    • Consolidated the Document Revision History section of each chapter into this chapter.
2021.07.23 21.2 Updated tx_am_gen_start and tx_am_gen_2x_ack signal directions in the following tables:
  • Reset Signals table.
  • Reset Signal Descriptions table.
2021.06.24 21.2 Initial document release.
Level Two Title