F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

Download PDF
ID 683872
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile Overview 2. F-Tile Architecture 3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5. F-Tile PMA/FEC Direct PHY Design Implementation 6. Supported Tools 7. Debugging F-Tile Transceiver Links 8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives 9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide A. Appendix
1. F-Tile Overview x
1.1. Device Family Support
2. F-Tile Architecture x
2.1. F-Tile Building Blocks 2.2. F-Tile Placement Rules 2.3. PMA Architecture 2.4. Clock Architecture
2.1. F-Tile Building Blocks x
2.1.1. FHT and FGT PMAs 2.1.2. 400G Hard IP and 200G Hard IP 2.1.3. PMA Data Rates 2.1.4. FEC Architecture 2.1.5. PCIe* Hard IP 2.1.6. Bonding Architecture 2.1.7. Deskew Logic 2.1.8. Embedded Multi-die Interconnect Bridge (EMIB) 2.1.9. IEEE 1588 Precision Time Protocol for Ethernet 2.1.10. Clock Networks 2.1.11. Reconfiguration Interfaces
2.2. F-Tile Placement Rules x
2.2.1. PMA-to-Fracture Mapping 2.2.2. Determining Which PMA to Map to Which Fracture 2.2.3. Hard IP Placement Rules 2.2.4. IEEE 1588 Precision Time Protocol Placement Rules 2.2.5. Topologies 2.2.6. FEC Placement Rules 2.2.7. Clock Rules and Restrictions 2.2.8. Bonding Placement Rules 2.2.9. Preserving Unused PMA Lanes
2.2.1. PMA-to-Fracture Mapping x
2.2.1.1. FHT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.2. FGT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.3. FGT-PMA-to-200G-Hard-IP-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture x
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT 2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT 2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT 2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT 2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT 2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
2.2.5. Topologies x
2.2.5.1. Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) Example 2.2.5.2. Topology 6a: 400G Hard IP with Mixed Transceiver Mode Example 2.2.5.3. Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP Example
2.2.8. Bonding Placement Rules x
2.2.8.1. Bonded Lanes Use Case 1 2.2.8.2. Bonded Lanes Use Case 2
2.3. PMA Architecture x
2.3.1. FHT PMA Architecture 2.3.2. FGT PMA Architecture
2.3.1. FHT PMA Architecture x
2.3.1.1. FHT Transmitter PMA Architecture 2.3.1.2. FHT Receiver PMA Architecture 2.3.1.3. FHT PMA Loopback Modes
2.3.1.1. FHT Transmitter PMA Architecture x
2.3.1.1.1. FHT Transmitter Buffer and Phase Generator 2.3.1.1.2. FHT Serializer 2.3.1.1.3. FHT Gray-Coder and Pre-Coder 2.3.1.1.4. FHT Data Pattern Generator and Verifier
2.3.1.2. FHT Receiver PMA Architecture x
2.3.1.2.1. FHT Receiver Buffer and Equalizer 2.3.1.2.2. CDR Block 2.3.1.2.3. FHT Deserializer
2.3.2. FGT PMA Architecture x
2.3.2.1. FGT Transmitter PMA Architecture 2.3.2.2. FGT Receiver PMA Architecture 2.3.2.3. FGT PMA Tuning 2.3.2.4. FGT PMA Loopback Modes
2.3.2.1. FGT Transmitter PMA Architecture x
2.3.2.1.1. FGT Transmitter Buffer and Phase Generator 2.3.2.1.2. FGT Serializer 2.3.2.1.3. FGT Gray-Coder and Pre-Coder 2.3.2.1.4. FGT Data Pattern Generator and Verifier
2.3.2.2. FGT Receiver PMA Architecture x
2.3.2.2.1. FGT Receiver Buffer and Equalizer 2.3.2.2.2. Control Unit 2.3.2.2.3. FGT Deserializer
2.4. Clock Architecture x
2.4.1. Reference Clock Network 2.4.2. Datapath Clock Network 2.4.3. System PLL 2.4.4. Datapath Clock Cadences
2.4.1. Reference Clock Network x
2.4.1.1. FHT Reference Clock Network 2.4.1.2. FGT and System PLL Reference Clock Network 2.4.1.3. FGT Primary PLL Configuration
2.4.1.2. FGT and System PLL Reference Clock Network x
2.4.1.2.1. FGT Reference Clock Receiver Analog Front End
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview 3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.3. Configuring the IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting Reset 3.9. Bonding Implementation 3.10. Independent Port Configurations 3.11. Configuration Registers 3.12. Configurable Quartus® Prime Software Settings 3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. Unsupported PMA/FEC Modes
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.2.1. Preset IP Parameter Settings
3.3. Configuring the IP x
3.3.1. General and Common Datapath Options 3.3.2. TX Datapath Options 3.3.3. RX Datapath Options 3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options 3.3.5. Avalon® Memory Mapped Interface Options 3.3.6. Register Map IP-XACT Support 3.3.7. Example Design Generation 3.3.8. Analog Parameter Options
3.3.1. General and Common Datapath Options x
3.3.1.1. FGT PMA Configuration Rules for SATA mode 3.3.1.2. FGT PMA Configuration Rules for GPON Mode
3.3.2. TX Datapath Options x
3.3.2.1. TX PMA interface Parameters
3.3.3. RX Datapath Options x
3.3.3.1. RX FGT PMA Interface Options
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. RS-FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. TX PMA Control Signals 3.4.7. RX PMA Status Signals 3.4.8. TX and RX PMA and Core Interface FIFO Signals 3.4.9. PMA Avalon® Memory Mapped Interface Signals 3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals x
3.4.10.1. Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per Interface
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath x
3.5.1. Parallel Data Mapping Information 3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations 3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1) 3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2) 3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations x
3.5.2.1. TX Parallel Data Mapping Information for SATA Protocol Mode for Different Configurations
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. FGT PMA Fractional Mode 3.6.5. FGT RX CDR Clock Output
3.6.5. FGT RX CDR Clock Output x
3.6.5.1. Dynamically Configure the FGT RX CDR Clock Output
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the tx_cadence_slow_clk_locked Port 3.7.2. Rate Match FIFO
3.8. Asserting Reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Reset Signals—Descriptions 3.8.5. Status Signals—Descriptions 3.8.6. Run-time Reset Sequence—TX 3.8.7. Run-time Reset Sequence—RX 3.8.8. Run-time Reset Sequence—TX + RX 3.8.9. Run-time Reset Sequence—TX with FEC
3.8.8. Run-time Reset Sequence—TX + RX x
3.8.8.1. Run-time Reset Sequence Approximate Time Durations
3.11. Configuration Registers x
3.11.1. PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. FHT PMA Register Map 3.11.3. FGT PMA Register Map 3.11.4. FEC Register Map 3.11.5. Lane Offset Address 3.11.6. Accessing Configuration Registers
3.11.6. Accessing Configuration Registers x
3.11.6.1. Accessing PMA and FEC Direct PHY Soft CSR Registers 3.11.6.2. Accessing FHT PMA Registers 3.11.6.3. Accessing FGT PMA Registers
3.11.6.2. Accessing FHT PMA Registers x
3.11.6.2.1. FHT PMA Register Address Range 0x40000 to 0x48000 3.11.6.2.2. FHT PMA Register Address Range 0x60000 to 0xF0030 3.11.6.2.3. FHT PMA Register Address 0xFFFFC
3.11.6.3. Accessing FGT PMA Registers x
3.11.6.3.1. FGT PMA Register Address Range 0x40000 to 0x48000 3.11.6.3.2. FGT PMA Register Address Range 0x62000 to 0x62004 3.11.6.3.3. FGT PMA Register Address Range 0x9003C to 0xF0028 3.11.6.3.4. FGT PMA Register Address 0xFFFFC
3.12. Configurable Quartus® Prime Software Settings x
3.12.1. FHT PMA Settings 3.12.2. FGT PMA Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing x
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.13.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP x
3.13.2.1. RTL Connection Example for JTAG to Avalon® Master Bridge Intel IP
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. FHT PMA 3.14.2. FGT PMA
3.14.1. FHT PMA x
3.14.1.1. Enabling Loopback 3.14.1.2. Enabling the PRBS Generator and Verifier for ES Devices Obtaining BER Values for Production Devices 3.14.1.4. TX Equalizer Settings 3.14.1.5. TX Error Injection 3.14.1.6. RX Reconvergence 3.14.1.7. Preserving Unused Lanes
3.14.2. FGT PMA x
3.14.2.1. Direct Register Method 3.14.2.2. FGT Attribute Access Method
3.14.2.1. Direct Register Method x
3.14.2.1.1. Direct Register Method Examples
3.14.2.2. FGT Attribute Access Method x
3.14.2.2.1. FGT Attribute Access Method Example 1 3.14.2.2.2. FGT Attribute Access Method Example 2 3.14.2.2.3. FGT Attribute Access Method Example 3
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for F-Tile Reference and System PLL Clocks Intel® FPGA IP Usage 4.5. Guidelines for Refclk #i is Active At and After Device Configuration 4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs
4.5. Guidelines for Refclk #i is Active At and After Device Configuration x
4.5.1. Guidelines for System PLL Reference Clock 4.5.2. Guidelines for FGT Reference Clock
4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs x
4.6.1. How to Read the Real-Time Lock Status of the FGT TX PLL 4.6.2. How to Read the Real-Time Lock Status of the FHT Lane TX PLL 4.6.3. How to Read the Real-Time Lock Status of the FHT Common TX PLL 4.6.4. How to Reset the FGT TX PLL 4.6.5. How to Reset the FHT Lane TX PLL and Common PLL
4.6.1. How to Read the Real-Time Lock Status of the FGT TX PLL x
4.6.1.1. How to Determine the TX PLL Your FGT Channel is Using
4.6.3. How to Read the Real-Time Lock Status of the FHT Common TX PLL x
4.6.3.1. How to Determine Which Common PLL Your FHT Channel is Using
5. F-Tile PMA/FEC Direct PHY Design Implementation x
5.1. Implementing the F-Tile PMA/FEC Direct PHY Design 5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5.5. Enabling Custom Cadence Generation Ports and Logic 5.6. Connecting the F-Tile PMA/FEC Direct PHY Design IP 5.7. Simulating the F-Tile PMA/FEC Direct PHY Design 5.8. F-Tile Interface Planning
5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
5.2.1. Setting General and Common Datapath Options 5.2.2. Setting TX Datapath Options 5.2.3. Setting RX Datapath Options
5.7. Simulating the F-Tile PMA/FEC Direct PHY Design x
5.7.1. PAM4 Encoding Schemes in Simulation
5.8. F-Tile Interface Planning x
5.8.1. F-Tile Interface Planner Usage Example
6. Supported Tools x
6.1. F-Tile Channel Placement Tool 6.2. F-Tile PMA and FEC Direct Port Mapping Calculator 6.3. F-Tile Clocking and Datapath Tool 6.4. F-Tile FGT TX Equalizer Tool
7. Debugging F-Tile Transceiver Links x
7.1. F-Tile Transceiver Toolkit GUI 7.2. F-Tile Transceiver Debugging Flow Walkthrough 7.3. Transceiver Toolkit Parameter Settings 7.4. Using F-Tile Multirate IPs with Transceiver Toolkit 7.5. Troubleshooting Common Errors 7.6. Transceiver Toolkit Scripts
7.1. F-Tile Transceiver Toolkit GUI x
7.1.1. Collection View
7.2. F-Tile Transceiver Debugging Flow Walkthrough x
7.2.1. Modifying the Design to Enable F-Tile Transceiver Debug 7.2.2. Programming the Design into an Intel FPGA 7.2.3. Loading the Design to the Transceiver Toolkit 7.2.4. Creating Transceiver Links 7.2.5. Running BER Tests 7.2.6. Running Eye Viewer Tests 7.2.7. Running Link Optimization Tests 7.2.8. Checking FEC Statistics 7.2.9. Vertical Bathtub Curve Measurements (VBCM) Data
7.3. Transceiver Toolkit Parameter Settings x
7.3.1. Dashboard
7.4. Using F-Tile Multirate IPs with Transceiver Toolkit x
7.4.1. F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP 7.4.2. F-Tile Ethernet Multirate Intel FPGA IP 7.4.3. Ethernet Subsystem Intel FPGA IP
7.6. Transceiver Toolkit Scripts x
7.6.1. Supported Transceiver Toolkit Scripts 7.6.2. Modifying the Scripts 7.6.3. Script Execution 7.6.4. Example of the Results in Tcl Console
A. Appendix x
A.1. Agilex™ 7 F-Tile OPNs A.2. OSC_CLK_1 QSF Assignment Requirement A.3. FGT Internal Serial Loopback Calibration Sequence for RX Manual Adaptation
1. F-Tile Overview
2. F-Tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. F-Tile PMA/FEC Direct PHY Design Implementation
6. Supported Tools
7. Debugging F-Tile Transceiver Links
8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide
A. Appendix

9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

Documet Vesio Quatus® Pime Vesio Chages
2024.11.04 24.3 Made the followig chages:
  • Updated the compliace specificatios i the F-Tile Suppoted FEC Modes ad Compliace Specificatios table i the FEC Achitectue sectio.
  • Added topology 16 i the F-Tile Topologies table i the Topologies sectio.
  • Removed the evese paallel loopback optio fom the FHT PMA Loopback Modes sectio.
  • Updated the FGT Gay-Code ad Pe-Code sectio with PAM4 ifomatio.
  • Updated the FGT Receive Buffe ad Equalize sectio with ifomatio about the cut-off fequecy.
  • Coected a typo i the fist equatio of tasmitte buffe equalize paamete combiatios fo the poductio devices i the FGT Tasmitte Buffe ad Phase Geeato sectio.
  • Updated the PMA Diect Suppoted Mode table fo the NRZ modulatio FGT PMA i PMA clockig mode with 16 bit PMA iteface width suppot.
  • Updated the FGT PMA Cofiguatio Rules fo GPON Mode sectio with additioal ifomatio about bust mode ad guidelies to utilize the LTR mode.
  • Updated the Eable Gay codig paamete desciptio i the RX FGT PMA Paametes table.
  • Updated the Eable fgt_x_cd_set_locktoef pot paamete desciptio i the RX FGT PMA Paametes table.
  • Updated the Eable fgt_x_set_locktoef pot ad Eable fgt_x_set_locktodata pot paamete desciptios i the RX FGT PMA Paametes table.
  • Updated the tx_pll_locked sigal desciptio i the TX ad RX Refeece Clock ad Clock Output Iteface Sigals ad Status Sigals—Desciptios sectios.
  • Updated the tx_pll_locked sigal desciptio i the Rutime-Reset-Sequece-TX ad Ru-time Reset Sequece—TX + RX sectios.
  • Added TX PLL Badwidth istace assigmet settigs i the FGT PMA Settigs sectio.
  • Removed evese paallel loopback settig fo FHT PMA fom the Loopback Mode Registe Settigs table.
  • Added ew topic Obtaiig BER Values fo Poductio Devices fo FHT PMA i the Hadwae Cofiguatio Usig the Avalo® Memoy-Mapped Iteface sectio.
  • Updated the e_efclk_fgt_i, efclk_fgt_eabled_i, ad efclock_status sigal desciptios i the F-Tile Refeece ad System PLL Clocks Itel® FPGA IP Pot List table.
  • Updated the Guidelies fo F-Tile Refeece ad System PLL Clocks Itel® FPGA IP Usage with equiemet to have oly oe F-Tile Refeece ad System PLL Clocks Itel® FPGA IP pe F-Tile.
  • Updated the Guidelies fo System PLL Refeece Clock sectio with ifomatio about the iput sigal e_efclk_fgt_i equiemets.
  • Updated the Guidelies fo FGT Refeece Clock sectio with ifomatio about the iput sigal e_efclk_fgt_i tasitio equiemets.
  • Added ew sectio Guidelies fo Obtaiig the Lock Status ad Resettig the FGT ad FHT TX PLLs i the Implemetig the F-Tile Refeece ad System PLL Clocks Itel FPGA IP chapte.
  • Updated the Simulatig the F-Tile PMA/FEC Diect PHY Desig sectio with additioal ifomatio about the simulatio setup ad files.
  • Updated the Toubleshootig Commo Eos sectio with ifomatio about toubleshootig the TX PMA Refeece Clock.
  • Updated Agilex 7 FPGAs ad SoCs Odeig Pat Numbe figue i Appedix A.1. Agilex 7 F-Tile OPNs.
  • Added Appedix A.3. FGT Iteal Seial Loopback Calibatio Sequece fo RX Maual Adaptatio.
2024.07.08 24.2 Made the followig chages:
  • Added top-level block diagam i the F-Tile Buildig Blocks sectio.
  • Updated the iteface type suppot fo the 2x PCIe x4 ad 1x PCIe x4 i the PCIe Had IP (Ge4, Ge3, Ge2, ad Ge1) Suppoted Cofiguatios table.
  • Updated the Clock Rules ad Restictios sectio with ifomatio about havig a stable ad uig efeece clock fo the FGT PMA.
  • Updated the Pesevig Uused PMA Laes sectio with ifomatio about assetig the PHY eset fo uused PMAs.
  • Updated the PMA Diect Mode Suppot table with a few PMA widths that ae ot suppoted.
  • Updated the FEC Diect Mode Suppot table with a few PMA widths that ae ot suppoted.
  • Updated the Geeal ad Commo Datapath Optios table with a ew paamete Eable pe PMA laes TX ad RX eady sigal.
  • Updated the RS-FEC (Reed Solomo Fowad Eo Coectio) Optios sectio with ifomatio about accessig the CWBIN0-3 egistes.
  • Updated the default value of the Eable FGT VSR mode paamete i the FGT RX Aalog Paamete Optios table.
  • Updated the TX ad RX Refeece Clock ad Clock Output Iteface Sigals table about the tx_pll_efclk_lik[N-1:0] ad x_cd_efclk_lik[N-1:0] sigal coectios.
  • Updated the Accessig Cofiguatio Registes sectio extesively ad added ew ifomatio ad sub-sectios.
  • Updated the VSR mode settigs i the FGT PMA Settigs topic i the Cofiguable Quatus Pime Softwae Settigs sectio.
  • Updated the Revese Paallel Loopback steps i the Diect Registe Method Examples topic with the eset ad FEC equiemets.
  • Added VSR mode settigs i the FGT Attibute Access Data Value 3 table i the FGT Attibute Access Method sectio.
  • Updated the F-Tile Refeece ad System PLL Clocks Itel FPGA IP Pot List table with additioal desciptio ad ecommedatio fo the disable_efclk_moito_i sigal ad a ote fo the avmm_clk, avmm_eset, ad out_coeclk_i sigals.
  • Updated the Guidelies fo F-Tile Refeece ad System PLL Clocks Itel FPGA IP Usage sectio with ifomatio about system PLL usage fo PCIe* ad othe potocols togethe.
  • Updated the Guidelies fo Refclk #i is Active At ad Afte Device Cofiguatio sectio.
  • Updated the Guidelies fo FGT Refeece Clock sectio with additioal ifomatio about the Refclk #i moito settig.
2024.04.01 24.1 Made the followig chages:
  • Added ew topic Device Family Suppot i F-Tile Oveview sectio with Agilex™ 9 suppot.
  • Added ew topic FGT PMA Cofiguatio Rules fo GPON Mode i Geeal ad Commo Datapath Optios sectio.
  • Updated fomula fo VCO Fequecy i FGT PMA Factioal Mode sectio.
  • Updated Dyamically Cofigue the FGT RX CDR Clock Output sectio with RX eset ACK equiemet step.
  • Added Hadwae Max time colum i Ru-time Reset Sequece Appoximate Time Duatios table.
  • Coected PMA laes to 8 fom 10 i Accessig FGT PMA Registes sectio examples.
  • Updated FGT PMA Settigs sectio with RX ivet P ad N ad TX ivet P ad N .qsf settigs.
  • Added footote to TX to RX Paallel Loopback i Diect Registe Method Examples topic.
  • Updated the steps i Measuig the Bit Eo Rate (BER) with FGT PMAs i Diect Registe Method Examples topic.
  • Updated the FGT Attibute Access Data Value 1 table i the FGT Attibute Access Method sectio.
  • Updated FGT Attibute Access Method Example 1 ad FGT Attibute Access Method Example 2 sectios with RX eset ACK equiemet step.
  • Added ote to Pot Coectio Guidelies betwee F-Tile Refeece ad System PLL Clocks Itel® FPGA IP ad F-Tile PMA/FEC Diect PHY Itel® FPGA IP table about o simulatio suppot.
  • Added ifomatio about how to set the Refclk #i is active at ad afte device cofiguatio paamete at device powe-up if a stable Refclk #i is ot peset i the Guidelies fo Refclk #i is Active At ad Afte Device Cofiguatio sectio.
  • Updated the Simulatig the F-Tile PMA/FEC Diect PHY Desig sectio with ifomatio about the top level etity istatiatio.
  • Added ew topic Dashboad i the Debuggig F-Tile Tasceive Liks sectio with ifomatio about the dashboad featue.
  • Added ew topic Usig the Multiate IPs with Tasceive Toolkit i the Debuggig F-Tile Tasceive Liks sectio with ifomatio about usig the tasceive toolkit with the F-Tile Multiate IPs.
  • Updated A.1 F-Tile Poductio Revisio OPNs i Appedix with ifomatio about poductio OPNs.
2024.01.24 23.4 Made the followig chages:
  • Updated the TX FHT PMA Paametes i Paamete Edito figue ad TX FHT PMA Paametes table i the TX Datapath Optios sectio.
  • Updated the RX FHT PMA Paametes i Paamete Edito figue ad RX FHT PMA Paametes table i the RX Datapath Optios sectio.
  • Updated desciptio of the Expot Refclk #0-9 fo use i use logic paametes i the F-Tile Refeece ad System PLL Clocks Itel® FPGA IP Paametes table.
  • Updated desciptio of the out_coeclk_i pot i the F-Tile Refeece ad System PLL Clocks Itel® FPGA IP Pot List table.
2023.12.04 23.4 Made the followig chages:
  • Added ote i F-Tile Buildig Blocks sectio about 200G had IP suppot i Agilex™ 7 device OPNs.
  • Updated NRZ ad PAM4 suppot ifomatio fo Quad0 i the Had IP Placemet Rules sectio.
  • Updated the fist ad secod bullet i Clock Rules ad Restictios sectio with additioal ifomatio.
  • Updated the FHT PMA Aalog Paamete figue ad the FHT RX Aalog Paamete table i the Aalog Paamete Optios sectio.
  • Removed hadwae max time ifomatio i the Ru-time Reset Sequece Appoximate Time Duatios table.
  • Removed PRBS 11 selectio value ad added PRBS 15 selectio value i the FGT Attibute Access Data Value 1 table.
  • Updated the F-Tile Refeece ad System PLL Clocks Itel FPGA IP Pot List table with ew pots ad eodeed the pot list.
  • Added ew topic Guidelies fo FGT Refeece Clock i the Guidelies fo Refclk #i is Active At ad Afte Device Cofiguatio sectio.
  • Added ote i F-Tile Chael Placemet Tool sectio about 200G had IP suppot i Agilex™ 7 device OPNs.
  • Added ifomatio about gay code settig fo FHT PMA i Ruig BER Tests topic.
  • Added ew topic Vetical Bathtub Cuve Measuemets Data about expotig the VBCM data.
  • Added ew paametes to the Tasceive Toolkit Paamete Settigs table.
  • Updated the paths i the Tasceive Toolkit Scipt Locatio table.
  • Added Appedix A.2 about the ew OSC_CLK_1 .qsf assigmet equiemet.
2023.10.02 23.3 Made the followig chages:
  • Updated bullet elated to 400G had IP suppot i Had IP Placemet Rules sectio.
  • Coected Numbe of PMAs to 12 fo 400G Had IP fo topology 14 i the F-Tile Topologies table.
  • Coected egistes to esistos i ote i FGT Refeece Clock Receive Aalog Fot Ed sectio.
  • Removed suppot fo USB potocol mode i seveal topics.
  • Added ew paametes Adaptatio mode ad Eable fgt_x_set_locktodata pot i the RX FGT PMA Paametes table.
  • Updated the values equatio fo Selected x_cd_divclk_lik0 souce paamete i the RX FGT PMA Paametes table.
  • Updated default settig to Eabled fo Eable FHT RX data pofile paamete i the RX FHT PMA Paametes table.
  • Removed efeeces to pot x_cd_divclk_lik1 i TX ad RX Refeece Clock ad Clock Output Iteface Sigals table.
  • Added ew sigal fgt_x_set_locktodata[N-1:0] to the RX PMA Status Sigals table.
  • Removed pot x_cd_divclk_lik1 fom Sigal ad Pot Refeece topic.
  • Updated Clock pots sectio with a ote about tx_clkout ad tx_clkout2 clock, ad x_clkout ad x_clkout2 clocks beig asychoous to each othe.
  • Added ew topic Aalog Paamete Optios about the Aalog Paametes tab i Cofiguig the IP sectio.
  • Added ew topics FGT RX CDR Clock Output ad Dyamically Cofigue the FGT RX CDR Clock Output i the Clockig sectio.
  • Updated the Idepedet Pot Cofiguatios sectio with additioal ifomatio.
  • Updated the Accessig FGT PMA Registes sectio with additioal ifomatio fo FGT PMA egistes with offset addess as 0x62000, 0x62004, o 0x62008.
  • Coected the TX ivet P ad N settig i the FHT PMA Settigs sectio.
  • Updated the Cofiguig the F-Tile PMA/FEC Diect PHY Itel FPGA IP fo Hadwae Testig sectio with additioal ifomatio.
  • Added ew table FGT Attibute Access Data Value 3 with opcode fo RX CDR clock i FGT Attibute Access Method sectio.
  • Added additioal desciptio fo Refclk fequecy #N paamete i the F-Tile Refeece ad System PLL Clocks Itel FPGA IP Paametes table.
  • Removed pots e_efclk_fgt_i[1:0] ad efclk_fgt_eabled_i fom the F-Tile Refeece ad System PLL Clocks Itel FPGA IP Pot List table.
  • Added pot efclock_status to the F-Tile Refeece ad System PLL Clocks Itel FPGA IP Pot List table.
  • Removed sectio Guidelies fo FGT Refeece Clock i the Implemetig the F-Tile Refeece ad System PLL Clocks Itel FPGA IP chapte.
  • Added additioal ifomatio about VHDL simulatio i step 7. of Simulatig the F-Tile PMA/FEC Diect PHY Desig sectio.
  • Added ew topic Checkig FEC Statistics i the F-Tile Tasceive Debuggig Flow Walkthough sectio.
  • Removed two M-Seies ES devices fom the OPN list i Appedix A.1.
2023.06.26 23.2 Made the followig chages:
  • Removed edudat figue fom FGT-PMA-to-400G-Had-IP-Factue Mappig sectio.
  • Removed the list of OPNs ad updated FGT Tasmitte Buffe ad Phase Geeato sectio with OPN list lik i Appedix A.1.
  • Added ew sectio FGT Refeece Clock Receive Aalog Fot Ed descibig temiatio equiemets fo the FGT efeece clock.
  • Updated desciptio fo the Eable fgt_x_cd_fast_feeze_sel pot ad Eable fgt_x_cd_feeze pot paametes i the RX FGT PMA Paametes table.
  • Added ote about how to access the CWBIN ad FEC egistes i the RS-FEC (Reed Solomo Fowad Eo Coectio) Optios sectio.
  • Added ote i desciptio colum of TX ad RX Refeece Clock ad Clock Output Iteface Sigals table fo x_clkout, x_clkout2, tx_clkout, tx_clkout2 sigals.
  • Updated desciptio fo fgt_x_cd_feeze[N-1: 0] sigal ad added ew sigal fgt_x_cd_fast_feeze_sel[N-1: 0] i RX PMA Status Sigals table.
  • Added fequecy age fo ecofig_xcv_clk ad ecofig_xcv<>_clk clock sigals i PMA Avalo® Memoy Mapped Iteface Sigals sectio.
  • Added fequecy age fo ecofig_pdp_clk ad ecofig_pdp<>_clk clock sigals i Datapath Avalo® Memoy Mapped Iteface Sigals sectio.
  • Removed the FGT Coe PLL Mode sectio as the mode is o loge suppoted i the Quatus® Pime Po Editio softwae.
  • Reogaized the cotet i the Cofiguable Quatus® Pime Softwae Settigs sectio.
  • Updated the FGT PMA Settigs sectio with valid paamete settigs fo TX Equalizatio ad RX Maual Equalizatio paametes.
  • Updated the Diect Registe Method Examples sectio with Measuig the Bit Eo Rate (BER) with FGT PMAs example ad a ote fo Iteal Seial Loopback ad Polaity Ivesio examples.
  • Updated the FGT Attibute Access Data Value 2 table with Get Status opcodes.
  • Removed paamete Refclk is available at device cofiguatio fom the F-Tile Refeece ad System PLL Clocks Itel® FPGA IP Paametes table.
  • Updated the F-Tile Refeece ad System PLL Clocks Itel® FPGA IP Paametes table with ew paametes Refclk # is active at ad afte device cofiguatio ad Expot Refclk # fo use i use logic
  • Updated the F-Tile Refeece ad System PLL Clocks Itel® FPGA IP Pot List table with the followig sigals; avmm_clk, avmm_eset, efclock_eady [2:0], e_efclk_fgt_i[1:0], efclk_fgt_eabled_i, ad out_coeclk_i.
  • Replaced sectio Guidelies to Idicate all System PLL Refeece Clocks ae Ready with ew sectio Guidelies fo Refclk #i is Active At ad Afte Device Cofiguatio.
  • Replaced sectio Example of Refeece Clock Availability at Device Pogammig with ew sectio Guidelies fo System PLL Refeece Clock.
  • Replaced sectio Example Flow to Idicate All System PLL Refeece Clocks ae Ready with ew sectio Guidelies fo FGT Refeece Clock.
  • Removed the chapte Implemetig the F-Tile Global Avalo® Memoy-Mapped Iteface Itel® FPGA IP fom the use guide as the IP is o loge suppoted i the Quatus® Pime Po Editio softwae.
  • Removed the list of OPNs ad updated F-Tile TX Equalize Tool sectio with OPN list lik i Appedix A.1.
  • Updated the Tcl File Name ad Path of scipts i the Suppoted Tasceive Toolkit Scipts sectio.
  • Added Appedix A.1 with list of F-tile Poductio Revisio ad Fimwae OPNs.
2023.04.03 23.1 Made the followig chages:
  • Updated the poduct family ame to Itel Agilex 7.
  • Added ew ifomatio about mixed tasceive mode (topology 6a) suppot i 400G Had IP ad 200G Had IP, PMA-to-Factue Mappig, ad Topologies sectios.
  • Updated Factue Type Used by Mode table with 200GbE-4 suppot i st_x16 ow.
  • Updated Clock Rules ad Restictios sectio with additioal equiemets fo a stable efeece clock.
  • Updated FGT Tasmitte PMA Equalize Paametes fo NRZ ad PAM4 Modes tables with additioal ifomatio ad missig default values.
  • Updated FGT Data Patte Geeato ad Veifie sectio with PRBS ad SSPR specificatio ifomatio.
  • Updated FGT PMA Loopback Modes sectio with additioal ifomatio about the vaious loopback modes.
  • Updated FGT PMA Loopback Modes figue with missig coectio.
  • Added desciptio about the 32-bit soft CWBIN coutes i RS-FEC (Reed Solomo Fowad Eo Coectio) Optios sectio.
  • Added ew paametes Iclude 32bit soft CWBIN coutes ad Recofig clock fequecy i RS-FEC Paametes table fo soft CWBIN coutes suppot.
  • Updated FGT PMA Factioal Mode sectio with coected ifomatio about settig the factioal mode.
  • Added ew sectio Accessig Cofiguatio Registes with detailed ifomatio about how to use the offset addess i the F-Tile PMA/FEC Diect PHY Itel® FPGA IP egiste map to access the egistes.
  • Coected Cofiguable Quatus® Pime Softwae Settigs sectio with FGT TX equalizatio example qsf values fo txeq_pe_tap_1 ad txeq_post_tap_1 ad added a ote i the sectio.
  • Updated the bypass RX auto adaptatio qsf assigmets ad added the RX maual equalizatio qsf assigmets i Cofiguable Quatus® Pime Softwae Settigs sectio.
  • Coected Diect Registe Method Example sectio with TX equalize pe-cuso 1 egiste ad TX equalize post-cuso 1 egiste addesses fo FGT PMA.
  • Added additioal FGT PMA settig examples i Diect Registe Method Examples sectio.
  • Added ote i FGT Attibute Access Method Example 2 sectio about egiste 0x90040[25:24] status values.
  • Updated F-Tile Refeece ad System PLL Clocks Itel® FPGA IP Paametes table with eamed Refclk is available at device cofiguatio paamete.
  • Updated Example Flow to Idicate All System PLL Refeece Clocks ae Ready sectio with Refclk is available at device cofiguatio paamete eamig.
  • Added Eable Debug Maste Edpoit o Global AVMM paamete to the F-Tile Global Avalo® Memoy-Mapped Iteface Itel® FPGA IP Paametes table.
  • Updated Hadwae Flow Usig the F-Tile Global Avalo® Memoy-Mapped Iteface Itel® FPGA IP sectio with usage ifomatio about Eable Debug Maste Edpoit o Global AVMM paamete.
  • Added ote i Ruig Eye Viewe Tests sectio about o suppot fo 2D Eye plots.
  • Added ew sectio Tasceive Toolkit Scipts with ifomatio about usig scipts available i the Quatus® Pime Po Editio softwae vesio 23.1 fo tasceive testig.
2023.01.25 22.4 Updated the FHT Loopback Mode figue with the coect Deseialize block locatio.
2022.12.19 22.4 Made the followig chages:
  • Updated Clock Rules ad Restictios sectio with additioal ifomatio about the efeece clocks ad a ew ote.
  • Updated FGT Tasmitte PMA Equalize Paametes fo NRZ ad PAM4 Modes table; eamed cuso to tap, ad updated the foototes.
  • Added equatios based o device OPN list fo the tasmitte buffe equalize paametes i the FGT Tasmitte Buffe ad Phase Geeato sectio.
  • Coected the peset amig i the F-Tile PMA/FEC Diect PHY Itel FPGA IP Available Paamete Pesets table i Peset IP Paamete Settigs sectio.
  • Updated the desciptio fo the PMA paallel clock fequecy paamete i Geeal ad Commo Datapath Optios table.
  • Updated the Show Peset Settigs figue i Example Desig Geeatio sectio.
  • Coected tx_coeclki ad x_coeclki sigal ames i Recommeded tx/x_coeclki Coectio ad tx/x_clkout2 Souce sectio.
  • Coected the k coute desciptios ad equatios i FGT PMA Factioal Mode sectio.
  • Added ew ifomatio about meetig jitte specificatios fo OTN/SDI ad i othe modes i FGT PMA Factioal Mode sectio.
  • Updated x_eady sigal desciptio i Reset Sigal Desciptios table.
  • Updated the steps ad figue i the Ru-time Reset Sequece—TX sectio.
  • Updated the steps ad figue i the Ru-time Reset Sequece—RX sectio.
  • Updated the steps ad figue i the Ru-time Reset Sequece—TX + RX sectio.
  • Updated colum heade fo FHT PMA Lae Numbe ad Offset Addess ad FGT PMA Lae Numbe ad Offset Addess tables i Lae Offset Addess sectio.
  • Updated desciptios fo calculatig the icemetal lae umbes fo the FHT PMA ad FGT PMA i Lae Offset Addess sectio.
  • Added .qsf settigs to bypass RX auto adaptatio i Cofiguable Itel Quatus Pime Softwae Settigs sectio.
  • Updated Guidelies fo F-Tile Refeece ad System PLL Clocks Itel FPGA IP Usage with additioal ifomatio about the system PLL efeece clock.
  • Updated Guidelies to Idicate all System PLL Refeece Clocks ae Ready with additioal ifomatio about usig the iteal clock to calibate ad cofigue the device, ifomatio about PCIe specificatio compliace, ad OPN device list that suppots Refclk is available at powe-o paamete.
  • Added additioal ifomatio i Example of Refeece Clock Availability at Device Pogammig sectio to claify the example.
  • Added tip fo step 5b. i Hadwae Flow Usig the F-Tile Global Avalo® Memoy-Mapped Iteface Itel® FPGA IP .
  • Added ew sectio Examples of Registe Access Usig the F-Tile Global Avalo® Memoy-Mapped Iteface Itel® FPGA IP with seveal topics with examples.
  • Updated the FGT tasmitte equalize cuso amig, added additioal tool lik fo vaious devices based o OPNs, ad updated figue i F-Tile TX Equalize Tool sectio.
  • Updated the FGT tasmitte equalize cuso amig, updated desciptios fo RX Ready ad PRBS locked paametes i Tasceive Toolkit Paamete Settigs table.
2022.11.03 22.3 Added a claifyig ote about the SATA ad USB potocol modes i sectios: FGT PMA Cofiguatio Rules fo SATA ad USB mode ad TX Paallel Data Mappig Ifomatio fo SATA ad USB Potocol Modes fo Diffeet Cofiguatios.
2022.09.26 22.3 Made the followig chages:
  • Updated FGT Tasmitte PMA Equalize Paametes fo NRZ ad PAM4 Modes table with total slice values fo diffeet OPNs.
  • Updated tx_eset_ack ad x_eset_ack sigal desciptios i the Reset Sigals ad Reset Sigal Desciptios tables.
  • Added ew paametes FGT PMA cofiguatio ules ad Eable simplified TX data iteface i Geeal ad Commo Datapath Optios table.
  • Added ew sectio FGT PMA Cofiguatio Rules fo SATA ad USB mode.
  • Added ew paametes Eable fgt_tx_beaco pot ad Eable Spead Spectum clockig i TX FGT Datapath Paametes table fo SATA ad USB suppot.
  • Added ew paametes Eable fgt_x_cd_fast_feeze_sel pot ad Eable fgt_x_cd_set_locktoef pot i RX FGT PMA Paametes table fo GPON suppot.
  • Updated desciptios fo Eable fgt_x_sigal_detect pot ad Eable fgt_x_sigal_detect_lfps pot paametes i RX FGT PMA Paametes table fo SATA ad USB suppot.
  • Coected TX PMA Status Sigals to TX PMA Cotol Sigals ad added ew sigal fgt_tx_pma_elecidle to the table.
  • Added ew sectio TX Paallel Data Mappig Ifomatio fo SATA ad USB Potocol Modes fo Diffeet Cofiguatios.
  • Updated ad eplaced PMA Avalo® memoy-mapped with Global Avalo® memoy-mapped iteface i Guidelies to Idicate all System PLL Refeece Clocks ae Ready sectio ad the examples.
  • Added additioal examples i step 6. of Hadwae Flow Usig the F-Tile Global Avalo Memoy-Mapped Iteface Itel FPGA IP sectio.
  • Updated Simulatig the F-Tile PMA/FEC Diect PHY Desig sectio with ifomatio about the auto-geeated file ames.
2022.06.24 22.2 Made the followig chages:
  • Updated F-Tile Suppoted FEC Modes ad Compliace Specificatios table with Fibe Chael 64G suppot ad added ote.
  • Claified fouth bullet i Clock Rules ad Restictios sectio with updated ules fo the FHT micocotolle efeece clock.
  • Added ew figue fo TX temiatio i FGT Tasmitte Buffe ad Phase Geeato.
  • Added ew figue fo RX temiatio i FGT Receive Buffe ad Equalize.
  • Added ew topic Registe Map IP-XACT Suppot i Cofiguig the IP sectio.
  • Added istuctios to simulate example desig usig VCS* MX ad Xcelium* simulatos i Example Desig Simulatio sectio.
  • Added ote fo tx_pll_efclk_lik ad x_cd_efclk_lik sigals i the TX ad RX Refeece Clock ad Clock Output Iteface Sigals table.
  • Updated FGT Attibute Access Method sectio with additioal ifomatio ad tables.
  • Added a ew example fo seial loopback eable ad disable i FGT Attibute Access Method sectio.
  • Deleted ote i step 7. of FGT Attibute Access Method Example 2.
  • Added ew paamete Refclk is available at powe-o i Implemetig the F-Tile Refeece ad System PLL Clocks Itel FPGA IP chapte.
  • Added ew sectio Guidelies to Idicate all System PLL Refeece Clocks ae Ready i Implemetig the F-Tile Refeece ad System PLL Clocks Itel FPGA IP chapte.
  • Updated step 5. of Hadwae Flow Usig the F-Tile Global Avalo Memoy-Mapped Iteface Itel FPGA IP.
  • Added FEC aligmet make ifomatio ad table i Implemetig a RS-FEC Diect Desig i the F-Tile PMA/FEC Diect PHY Itel FPGA IP
  • Added data scamblig ad de-scamblig ifomatio fo FEC i Implemetig a RS-FEC Diect Desig i the F-Tile PMA/FEC Diect PHY Itel FPGA IP.
  • Updated Ruig Eye Viewe Tests with a additioal step ad figues.
  • Added ifomatio about Autosweep i Ruig Lik Optimizatio Tests.
2022.03.28 22.1 Made the followig chages:
  • Claified thid bullet i Clock Rules ad Restictios sectio with updated ules fo the system PLL efeece clock.
  • Added ote about bodig ules i the Bodig Placemet Rules sectio.
  • Added ew topic Tuig the Factioal Value i Factioal Mode i the FGT PMA Factioal Mode sectio.
  • Added PMA Recofiguatio Iteface colum i the Reset Sigals—Block Level table ad added a ote about the ecofig_xcv_eset sigal usage.
  • Updated TX equalizatio mai tap example settig fo FHT PMA i Cofiguable Itel Quatus Pime Softwae Settigs sectio.
  • Added FGT Attibute Access Method Example 2 i FGT Attibute Access Method sectio fo TX ad RX polaity ivesio.
  • Updated Ruig BER Tests sectio with ifomatio about the Actios sub-meu.
  • Updated Ruig Eye Viewe Tests sectio with detailed desciptio about usig the Eye Viewe tool fo eye height measuemet fo the FGT PMA.
2021.12.15 21.4 Made the followig chages:
  • Updated Icemet ad Decemet Size colum i the FGT Tasmitte PMA Equalize Paametes fo NRZ ad PAM4 Modes table.
  • Added footote fo System PLL fequecy desciptio i Geeal ad Commo Datapath Optios table.
  • Added footote fo TX FGT PLL efeece clock fequecy desciptio i TX FGT Datapath Paametes table.
  • Added footote to TX ad RX Refeece Clock ad Clock Output Iteface Sigals table.
  • Removed ote fo Eable x_cd_divclk_lik0 pot ad Eable x_cd_divclk_lik1 pot paametes i the RX FGT PMA Paametes table.
  • Updated Example Desig Geeatio with RS-FEC example desig ifomatio.
  • Added ote to Clockig sectio i Implemetig the F-Tile PMA/FEC Diect PHY Itel FPGA IP chapte.
  • Added RX ivet P ad N, RX temiatio, TX ivet P ad N, TX temiatio, TX out tistate eable ad TX equalizatio qsf settigs fo FHT PMA i Cofiguable Itel Quatus Pime Softwae Settigs sectio.
  • Removed RX temiatio mode select qsf settig fo FGT PMA i Cofiguable Itel Quatus Pime Softwae Settigs sectio.
  • Added TX equalizatio qsf settig fo FGT PMA i Cofiguable Itel Quatus Pime Softwae Settigs sectio.
  • Updated steps 4a, 6, 8a, 10c, 13c, 14b ad 14c i the FGT Attibute Access Method Example topic.
  • Reogaized ifomatio i the Implemetig the F-Tile Refeece ad System PLL Clocks Itel FPGA IP chapte to make it cleae.
  • Removed ote fo Eable FGT CDR Output #0 ad Eable FGT CDR Output #1 paametes i the F-Tile Refeece ad System PLL Clocks Itel FPGA IP Paametes table.
  • Added desciptio to specify qsf locatio assigmet fo the out_cdclk_i pot i the F-Tile Refeece ad System PLL Clocks Itel FPGA IP Pot List table.
  • Added ew sectio Guidelies fo F-Tile Refeece ad System PLL Clocks Itel FPGA IP Usage.
  • Updated step 5 of the Hadwae Flow Usig the F-Tile Global Avalo Memoy-Mapped Iteface Itel FPGA IP sectio.
  • Updated F-tile PMA/FEC Diect PHY Desig Implemetatio chapte to emove efeeces to desig example.
  • Updated F-Tile Tasceive Toolkit GUI, Collectio View Tab of the F-Tile Tasceive Toolkit GUI, Toolkit Exploe, Example BER Test Setup ad Results fo the FGT PMA figues i the Debuggig F-Tile Tasceive Liks chapte.
  • Updated PMA amig i the Ruig BER Tests sectio.
  • Updated Tasceive Toolkit Paamete Settigs table with ew ifomatio.
  • Updated Ceatig Tasceive Liks sectio with Impot Collectios ad Expot Collectios details.
  • Added footote fo TX Equalizatio Paametes i the Tasceive Toolkit Paamete Settigs table.
2021.10.15 21.3 Made the followig chages:
  • Updated the Pesevig Uused PMA Laes sectio.
  • Updated the Numbe of system copies paamete i Geeal ad Commo Datapath Optios table.
  • Added Eable Coe PLL mode paamete i TX FGT Datapath table.
  • Updated Eable FHT RX data pofile paamete i RX FHT PMA Paametes table.
  • Updated the Example Desig Geeatio topic i the Cofiguig the IP sectio.
  • Updated paamete ames to match with GUI ames i Avalo® Memoy Mapped Iteface Paametes table.
  • Added desciptio fo Numbe of system copies paamete i the Sigal ad Pot Refeece sectio.
  • Updated desciptio of the FGT PMA Factioal Mode sectio.
  • Added ew topic Ru-time Reset Sequece Appoximate Time Duatio i Ru-time Reset Sequece—TX + RX sectio.
  • Updated step 4 owads i the Ru-time Reset Sequece—TX with FEC sectio
  • Updated desciptio of the Lae Offset Addess sectio.
  • Added ew topic Logical Avalo Memoy-Mapped Pot Idexig i Cofiguatio Registes sectio.
  • Updated steps i FGT Attibute Access Method Example.
  • Added footote that ETHERNET_FREQ_805_322 is ot suppoted i sectio Mode of System PLL - System PLL Refeece Clock ad Output Fequecies.
  • Added ew sectio Hadwae Flow Usig the F-Tile Global Avalo Memoy-Mapped Iteface Itel FPGA IP i Implemetig the F-Tile Global Avalo Memoy-Mapped Iteface Itel FPGA IP chapte.
  • Added the followig ew sectios i the F-tile PMA/FEC Diect PHY Desig Example Implemetatio chapte.
    • Implemetig a RS-FEC Diect Desig i the F-Tile PMA/FEC Diect PHY Itel FPGA IP.
    • PAM4 Ecodig Schemes i Simulatio.
    • F-tile Iteface Plae Desig Example.
    • Updated the Simulatig the F-tile PMA/FEC Diect PHY Desig Example sectio.
  • Added ad updated the followig sectios i the Suppoted Tools chapte.
    • F-Tile PMA ad FEC Diect Pot Mappig Calculato.
    • F-Tile Clockig ad Datapath Tool.
    • F-Tile TX Equalize Tool.
  • Added ew chapte Debuggig F-Tile Tasceive Liks.
2021.08.18 21.2
  • Added the followig ew sectios ad updated table i Implemetig the F-Tile PMA/FEC Diect PHY Itel® FPGA IP chapte:
    • Cofiguatio Registes.
    • Cofiguable Quatus® Pime Softwae Settigs.
    • Cofiguig the F-Tile PMA/FEC Diect PHY Itel® FPGA IP fo Hadwae Testig.
    • Hadwae Cofiguatio Usig the Avalo® Memoy-Mapped Iteface.
    • Added loopback mode i TX FHT PMA Paametes table.
  • Added ew topic i F-Tile Placemet Rules sectio i the F-Tile Achitectue chapte:
    • Pesevig Uused PMA Laes.
  • Added ew chapte Suppoted Tools.
  • Added ew chapte Documet Revisio Histoy fo F-tile Achitectue ad PMA ad FEC Diect PHY IP Use Guide.
    • Cosolidated the Documet Revisio Histoy sectio of each chapte ito this chapte.
2021.07.23 21.2 Updated tx_am_ge_stat ad tx_am_ge_2x_ack sigal diectios i the followig tables:
  • Reset Sigals table.
  • Reset Sigal Desciptios table.
2021.06.24 21.2 Iitial documet elease.
Level Two Title