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Ixiasoft
1. F-Tile Overview
2. F-Tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. F-Tile PMA/FEC Direct PHY Design Implementation
6. Supported Tools
7. Debugging F-Tile Transceiver Links
8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide
A. Appendix
2.1.1. FHT and FGT PMAs
2.1.2. 400G Hard IP and 200G Hard IP
2.1.3. PMA Data Rates
2.1.4. FEC Architecture
2.1.5. PCIe* Hard IP
2.1.6. Bonding Architecture
2.1.7. Deskew Logic
2.1.8. Embedded Multi-die Interconnect Bridge (EMIB)
2.1.9. IEEE 1588 Precision Time Protocol for Ethernet
2.1.10. Clock Networks
2.1.11. Reconfiguration Interfaces
2.2.1. PMA-to-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture
2.2.3. Hard IP Placement Rules
2.2.4. IEEE 1588 Precision Time Protocol Placement Rules
2.2.5. Topologies
2.2.6. FEC Placement Rules
2.2.7. Clock Rules and Restrictions
2.2.8. Bonding Placement Rules
2.2.9. Preserving Unused PMA Lanes
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT
2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT
2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT
2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT
2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT
2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP
3.3. Configuring the IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting Reset
3.9. Bonding Implementation
3.10. Independent Port Configurations
3.11. Configuration Registers
3.12. Configurable Quartus® Prime Software Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.3.1. General and Common Datapath Options
3.3.2. TX Datapath Options
3.3.3. RX Datapath Options
3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options
3.3.5. Avalon® Memory Mapped Interface Options
3.3.6. Register Map IP-XACT Support
3.3.7. Example Design Generation
3.3.8. Analog Parameter Options
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. RS-FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. TX PMA Control Signals
3.4.7. RX PMA Status Signals
3.4.8. TX and RX PMA and Core Interface FIFO Signals
3.4.9. PMA Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.5.1. Parallel Data Mapping Information
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations
3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1)
3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2)
3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Reset Signals—Descriptions
3.8.5. Status Signals—Descriptions
3.8.6. Run-time Reset Sequence—TX
3.8.7. Run-time Reset Sequence—RX
3.8.8. Run-time Reset Sequence—TX + RX
3.8.9. Run-time Reset Sequence—TX with FEC
5.1. Implementing the F-Tile PMA/FEC Direct PHY Design
5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
5.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
5.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5.5. Enabling Custom Cadence Generation Ports and Logic
5.6. Connecting the F-Tile PMA/FEC Direct PHY Design IP
5.7. Simulating the F-Tile PMA/FEC Direct PHY Design
5.8. F-Tile Interface Planning
7.2.1. Modifying the Design to Enable F-Tile Transceiver Debug
7.2.2. Programming the Design into an Intel FPGA
7.2.3. Loading the Design to the Transceiver Toolkit
7.2.4. Creating Transceiver Links
7.2.5. Running BER Tests
7.2.6. Running Eye Viewer Tests
7.2.7. Running Link Optimization Tests
7.2.8. Checking FEC Statistics
7.2.9. Vertical Bathtub Curve Measurements (VBCM) Data
Visible to Intel only — GUID: nbd1614297401943
Ixiasoft
4.2. IP Port List
The following table lists the ports for the IP; all ports are 1-bit wide.
Port Name | Direction | Description |
---|---|---|
FHT | ||
in_refclk_fht_i | Input | FHT reference clock input port. Must be mapped to device reference clock pin. Maximum of 2 (i = 0 to 1) ports of this type. |
out_fht_cmmpll_clk_i | Output | FHT common PLL output port. Must be connected to protocol IPs, connected to FHT building-block. There can be a maximum of 2(i = 0 to 1) ports of this type. |
FGT and System PLL | ||
in_refclk_fgt_i | Input | FGT and system PLL reference clock input port. Must be mapped to device reference clock pin. This reference clock port can be connected to FGT PMA, system PLL or both. There can be a maximum of 10 (i = 0 to 9) ports of this type. |
avmm_clk | Input |
Avalon® memory-mapped interface clock. This port is only available when at least one of Refclk #i is active at and after device configuration is set as Off. Altera recommends 100 to 250 MHz for this clock.
Note: Starting with Quartus® Prime Pro Edition software version 24.2, this port no longer functions and serves as a dummy port for backward compatibility.
|
avmm_reset | Input |
Avalon® memory-mapped interface reset. This port is only available when at least one of Refclk #i is active at and after device configuration is set as Off.
Note: Starting with Quartus® Prime Pro Edition software version 24.2, this port no longer functions and serves as a dummy port for backward compatibility.
|
FGT | ||
out_refclk_fgt_i | Output | FGT Refclk output port. Must be connected to protocol IPs, connected to FGT building-block. There can be a maximum of 10 (i = 0 to 9) ports of this type. |
en_refclk_fgt_i | Input |
FGT reference clock status control signal. This port is only available when the corresponding Refclk #i is active at and after device configuration set as Off. There can be a maximum of 10 (i = 0 to 9) ports of this type.
|
disable_refclk_monitor_i | Input |
FGT reference clock monitor control signal. This port is only available when the corresponding Refclk #i is used by the FGT PMA or the system PLL. There can be a maximum of 10 (i = 0 to 9) ports of this type.
When the Refclk #i becomes inactive, to prevent FGT PMA lane performance from degradation the following conditions occur:
|
refclk_fgt_enabled_i | Output |
FGT reference clock status signal. This port is only available when the corresponding Refclk #i is active at and after device configuration is set to Off. There can be a maximum of 10 (i = 0 to 9) ports of this type.
|
in_cdrclk_i | Input | Input port for FGT reference clock configured as CDR output. This must be connected to protocol IP output CDR port. There can be a maximum of 2 (i = 0 to 1) ports of this type. |
out_cdrclk_i | Output | Output port for FGT reference clock configured as CDR output. This must be connected to one of two FGT reference clock pins that can be configured as CDR outputs. You must specify the location assignment in the Quartus® Prime Pro Edition software qsf settings file for correct functionality. There can be a maximum of 2 (i = 0 to 1) ports of this type. |
out_coreclk_i | Output |
FGT reference clock output port for user logic. This port is only available when the corresponding Export Refclk #i for use in user logic is set to On.
Note: This signal cannot directly feed the reference clock of the IOPLL Intel FPGA IP.
|
System PLL | ||
out_systempll_clk_i | Output | Output port of system PLL. This must be connected to system PLL clock input of protocol IP. There can be a maximum of 3 (i = 0 to 2) ports of this type. |
out_systempll_synthlock_i | Output | System PLL lock status port which indicates if system PLL is locked to incoming reference clock. There can be a maximum of 3 (i = 0 to 2) ports of this type. You can use this port as a status or debug signal. |
refclock_ready [2:0] | Input |
System PLL reference clock status control signal. This port is only available when all the enabled system PLL's corresponding Refclk #i is active at and after device configuration are set as Off.
When system PLL #i is disabled, bit[i] can be any value and does not matter. When system PLL #i is enabled, after the reference clock is available, you must assert bit[i] to notify the system PLL to start locking to the incoming reference clock. |
refclock_status | Output |
System PLL reference clock status signal. This port is only available when all the enabled system PLL's corresponding Refclk #i is active at and after device configuration are set to Off. After you assert the refclock_ready signal, the system PLL starts to phase-lock to the reference clock and outputs its status.
|