F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

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ID 683872
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile Overview 2. F-Tile Architecture 3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5. F-Tile PMA/FEC Direct PHY Design Implementation 6. Supported Tools 7. Debugging F-Tile Transceiver Links 8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives 9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide A. Appendix
1. F-Tile Overview x
1.1. Device Family Support
2. F-Tile Architecture x
2.1. F-Tile Building Blocks 2.2. F-Tile Placement Rules 2.3. PMA Architecture 2.4. Clock Architecture
2.1. F-Tile Building Blocks x
2.1.1. FHT and FGT PMAs 2.1.2. 400G Hard IP and 200G Hard IP 2.1.3. PMA Data Rates 2.1.4. FEC Architecture 2.1.5. PCIe* Hard IP 2.1.6. Bonding Architecture 2.1.7. Deskew Logic 2.1.8. Embedded Multi-die Interconnect Bridge (EMIB) 2.1.9. IEEE 1588 Precision Time Protocol for Ethernet 2.1.10. Clock Networks 2.1.11. Reconfiguration Interfaces
2.2. F-Tile Placement Rules x
2.2.1. PMA-to-Fracture Mapping 2.2.2. Determining Which PMA to Map to Which Fracture 2.2.3. Hard IP Placement Rules 2.2.4. IEEE 1588 Precision Time Protocol Placement Rules 2.2.5. Topologies 2.2.6. FEC Placement Rules 2.2.7. Clock Rules and Restrictions 2.2.8. Bonding Placement Rules 2.2.9. Preserving Unused PMA Lanes
2.2.1. PMA-to-Fracture Mapping x
2.2.1.1. FHT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.2. FGT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.3. FGT-PMA-to-200G-Hard-IP-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture x
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT 2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT 2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT 2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT 2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT 2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
2.2.5. Topologies x
2.2.5.1. Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) Example 2.2.5.2. Topology 6a: 400G Hard IP with Mixed Transceiver Mode Example 2.2.5.3. Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP Example
2.2.8. Bonding Placement Rules x
2.2.8.1. Bonded Lanes Use Case 1 2.2.8.2. Bonded Lanes Use Case 2
2.3. PMA Architecture x
2.3.1. FHT PMA Architecture 2.3.2. FGT PMA Architecture
2.3.1. FHT PMA Architecture x
2.3.1.1. FHT Transmitter PMA Architecture 2.3.1.2. FHT Receiver PMA Architecture 2.3.1.3. FHT PMA Loopback Modes
2.3.1.1. FHT Transmitter PMA Architecture x
2.3.1.1.1. FHT Transmitter Buffer and Phase Generator 2.3.1.1.2. FHT Serializer 2.3.1.1.3. FHT Gray-Coder and Pre-Coder 2.3.1.1.4. FHT Data Pattern Generator and Verifier
2.3.1.2. FHT Receiver PMA Architecture x
2.3.1.2.1. FHT Receiver Buffer and Equalizer 2.3.1.2.2. CDR Block 2.3.1.2.3. FHT Deserializer
2.3.2. FGT PMA Architecture x
2.3.2.1. FGT Transmitter PMA Architecture 2.3.2.2. FGT Receiver PMA Architecture 2.3.2.3. FGT PMA Tuning 2.3.2.4. FGT PMA Loopback Modes
2.3.2.1. FGT Transmitter PMA Architecture x
2.3.2.1.1. FGT Transmitter Buffer and Phase Generator 2.3.2.1.2. FGT Serializer 2.3.2.1.3. FGT Gray-Coder and Pre-Coder 2.3.2.1.4. FGT Data Pattern Generator and Verifier
2.3.2.2. FGT Receiver PMA Architecture x
2.3.2.2.1. FGT Receiver Buffer and Equalizer 2.3.2.2.2. Control Unit 2.3.2.2.3. FGT Deserializer
2.4. Clock Architecture x
2.4.1. Reference Clock Network 2.4.2. Datapath Clock Network 2.4.3. System PLL 2.4.4. Datapath Clock Cadences
2.4.1. Reference Clock Network x
2.4.1.1. FHT Reference Clock Network 2.4.1.2. FGT and System PLL Reference Clock Network 2.4.1.3. FGT Primary PLL Configuration
2.4.1.2. FGT and System PLL Reference Clock Network x
2.4.1.2.1. FGT Reference Clock Receiver Analog Front End
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview 3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.3. Configuring the IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting Reset 3.9. Bonding Implementation 3.10. Independent Port Configurations 3.11. Configuration Registers 3.12. Configurable Quartus® Prime Software Settings 3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. Unsupported PMA/FEC Modes
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.2.1. Preset IP Parameter Settings
3.3. Configuring the IP x
3.3.1. General and Common Datapath Options 3.3.2. TX Datapath Options 3.3.3. RX Datapath Options 3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options 3.3.5. Avalon® Memory Mapped Interface Options 3.3.6. Register Map IP-XACT Support 3.3.7. Example Design Generation 3.3.8. Analog Parameter Options
3.3.1. General and Common Datapath Options x
3.3.1.1. FGT PMA Configuration Rules for SATA mode 3.3.1.2. FGT PMA Configuration Rules for GPON Mode
3.3.2. TX Datapath Options x
3.3.2.1. TX PMA interface Parameters
3.3.3. RX Datapath Options x
3.3.3.1. RX FGT PMA Interface Options
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. RS-FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. TX PMA Control Signals 3.4.7. RX PMA Status Signals 3.4.8. TX and RX PMA and Core Interface FIFO Signals 3.4.9. PMA Avalon® Memory Mapped Interface Signals 3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals x
3.4.10.1. Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per Interface
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath x
3.5.1. Parallel Data Mapping Information 3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations 3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1) 3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2) 3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations x
3.5.2.1. TX Parallel Data Mapping Information for SATA Protocol Mode for Different Configurations
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. FGT PMA Fractional Mode 3.6.5. FGT RX CDR Clock Output
3.6.5. FGT RX CDR Clock Output x
3.6.5.1. Dynamically Configure the FGT RX CDR Clock Output
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the tx_cadence_slow_clk_locked Port 3.7.2. Rate Match FIFO
3.8. Asserting Reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Reset Signals—Descriptions 3.8.5. Status Signals—Descriptions 3.8.6. Run-time Reset Sequence—TX 3.8.7. Run-time Reset Sequence—RX 3.8.8. Run-time Reset Sequence—TX + RX 3.8.9. Run-time Reset Sequence—TX with FEC
3.8.8. Run-time Reset Sequence—TX + RX x
3.8.8.1. Run-time Reset Sequence Approximate Time Durations
3.11. Configuration Registers x
3.11.1. PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. FHT PMA Register Map 3.11.3. FGT PMA Register Map 3.11.4. FEC Register Map 3.11.5. Lane Offset Address 3.11.6. Accessing Configuration Registers
3.11.6. Accessing Configuration Registers x
3.11.6.1. Accessing PMA and FEC Direct PHY Soft CSR Registers 3.11.6.2. Accessing FHT PMA Registers 3.11.6.3. Accessing FGT PMA Registers
3.11.6.2. Accessing FHT PMA Registers x
3.11.6.2.1. FHT PMA Register Address Range 0x40000 to 0x48000 3.11.6.2.2. FHT PMA Register Address Range 0x60000 to 0xF0030 3.11.6.2.3. FHT PMA Register Address 0xFFFFC
3.11.6.3. Accessing FGT PMA Registers x
3.11.6.3.1. FGT PMA Register Address Range 0x40000 to 0x48000 3.11.6.3.2. FGT PMA Register Address Range 0x62000 to 0x62004 3.11.6.3.3. FGT PMA Register Address Range 0x9003C to 0xF0028 3.11.6.3.4. FGT PMA Register Address 0xFFFFC
3.12. Configurable Quartus® Prime Software Settings x
3.12.1. FHT PMA Settings 3.12.2. FGT PMA Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing x
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.13.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP x
3.13.2.1. RTL Connection Example for JTAG to Avalon® Master Bridge Intel IP
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. FHT PMA 3.14.2. FGT PMA
3.14.1. FHT PMA x
3.14.1.1. Enabling Loopback 3.14.1.2. Enabling the PRBS Generator and Verifier for ES Devices 3.14.1.3. Obtaining BER Values for Production Devices 3.14.1.4. TX Equalizer Settings 3.14.1.5. TX Error Injection 3.14.1.6. RX Reconvergence 3.14.1.7. Preserving Unused Lanes
3.14.2. FGT PMA x
3.14.2.1. Direct Register Method 3.14.2.2. FGT Attribute Access Method
3.14.2.1. Direct Register Method x
3.14.2.1.1. Direct Register Method Examples
3.14.2.2. FGT Attribute Access Method x
3.14.2.2.1. FGT Attribute Access Method Example 1 3.14.2.2.2. FGT Attribute Access Method Example 2 3.14.2.2.3. FGT Attribute Access Method Example 3
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for F-Tile Reference and System PLL Clocks Intel® FPGA IP Usage 4.5. Guidelines for Refclk #i is Active At and After Device Configuration 4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs
4.5. Guidelines for Refclk #i is Active At and After Device Configuration x
4.5.1. Guidelines for System PLL Reference Clock 4.5.2. Guidelines for FGT Reference Clock
4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs x
4.6.1. How to Read the Real-Time Lock Status of the FGT TX PLL 4.6.2. How to Read the Real-Time Lock Status of the FHT Lane TX PLL 4.6.3. How to Read the Real-Time Lock Status of the FHT Common TX PLL 4.6.4. How to Reset the FGT TX PLL 4.6.5. How to Reset the FHT Lane TX PLL and Common PLL
4.6.1. How to Read the Real-Time Lock Status of the FGT TX PLL x
4.6.1.1. How to Determine the TX PLL Your FGT Channel is Using
4.6.3. How to Read the Real-Time Lock Status of the FHT Common TX PLL x
4.6.3.1. How to Determine Which Common PLL Your FHT Channel is Using
5. F-Tile PMA/FEC Direct PHY Design Implementation x
5.1. Implementing the F-Tile PMA/FEC Direct PHY Design 5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5.5. Enabling Custom Cadence Generation Ports and Logic 5.6. Connecting the F-Tile PMA/FEC Direct PHY Design IP 5.7. Simulating the F-Tile PMA/FEC Direct PHY Design 5.8. F-Tile Interface Planning
5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
5.2.1. Setting General and Common Datapath Options 5.2.2. Setting TX Datapath Options 5.2.3. Setting RX Datapath Options
5.7. Simulating the F-Tile PMA/FEC Direct PHY Design x
5.7.1. PAM4 Encoding Schemes in Simulation
5.8. F-Tile Interface Planning x
5.8.1. F-Tile Interface Planner Usage Example
6. Supported Tools x
6.1. F-Tile Channel Placement Tool 6.2. F-Tile PMA and FEC Direct Port Mapping Calculator 6.3. F-Tile Clocking and Datapath Tool 6.4. F-Tile FGT TX Equalizer Tool
7. Debugging F-Tile Transceiver Links x
7.1. F-Tile Transceiver Toolkit GUI 7.2. F-Tile Transceiver Debugging Flow Walkthrough 7.3. Transceiver Toolkit Parameter Settings 7.4. Using F-Tile Multirate IPs with Transceiver Toolkit 7.5. Troubleshooting Common Errors 7.6. Transceiver Toolkit Scripts
7.1. F-Tile Transceiver Toolkit GUI x
7.1.1. Collection View
7.2. F-Tile Transceiver Debugging Flow Walkthrough x
7.2.1. Modifying the Design to Enable F-Tile Transceiver Debug 7.2.2. Programming the Design into an Intel FPGA 7.2.3. Loading the Design to the Transceiver Toolkit 7.2.4. Creating Transceiver Links 7.2.5. Running BER Tests 7.2.6. Running Eye Viewer Tests 7.2.7. Running Link Optimization Tests 7.2.8. Checking FEC Statistics 7.2.9. Vertical Bathtub Curve Measurements (VBCM) Data
7.3. Transceiver Toolkit Parameter Settings x
7.3.1. Dashboard
7.4. Using F-Tile Multirate IPs with Transceiver Toolkit x
7.4.1. F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP 7.4.2. F-Tile Ethernet Multirate Intel FPGA IP 7.4.3. Ethernet Subsystem Intel FPGA IP
7.6. Transceiver Toolkit Scripts x
7.6.1. Supported Transceiver Toolkit Scripts 7.6.2. Modifying the Scripts 7.6.3. Script Execution 7.6.4. Example of the Results in Tcl Console
A. Appendix x
A.1. Agilex™ 7 F-Tile OPNs A.2. OSC_CLK_1 QSF Assignment Requirement A.3. FGT Internal Serial Loopback Calibration Sequence for RX Manual Adaptation
1. F-Tile Overview
2. F-Tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. F-Tile PMA/FEC Direct PHY Design Implementation
6. Supported Tools
7. Debugging F-Tile Transceiver Links
8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide
A. Appendix

A.3. FGT Internal Serial Loopback Calibration Sequence for RX Manual Adaptation

For a FGT RX manual adaptation design, the optimal flow to enable the internal serial loopback requires you to configure an additional sequence of calibration registers.
The following table summarizes the list of registers that you need to set during serial internal loopback (SILB) enablement.
Table 122.  Calibration Registers
Register ID Register Address Value
0 0x41450[18] 0x1
1 0x41584[15:14] 0x1
2 0x415dc[29:28] 0x0
3 0x41674[28:27] 0x0
0x41674[30:29] 0x0
4 0x4167c[23:22] 0x3
0x4167c[25:24] 0x3
5 0x41680[31:30] 0x0
6 0x41684[28:27] 0x0
0x41684[31:30] 0x0
7 0x41758[30:29] 0x3
8 0x4175c[15:14] 0x3
0x4175c[17:16] 0x3
9 0x41808[16:15] 0x2
10 0x41938[3:2] 0x1
0x41938[11:10] 0x1
0x41938[13:12] 0x1
0x41938[15:14] 0x1
0x41938[9:8] 0x1
0x41938[19:18] 0x3
0x41938[27:26] 0x3
0x41938[29:28] 0x3
0x41938[31:30] 0x3
0x41938[25:24] 0x3
11 0x4193c[3:2] 0x3
0x4193c[5:4] 0x3
0x4193c[7:6] 0x3
0x4193c[1:0] 0x3
12 0x41960[29] 0x1
13 0x419b4[28] 0x1
14 0x419b8[27] 0x1
15 0x41a88[28:27] 0x1
0x41a88[30:29] 0x3
16 0x41a8c[28:27] 0x1
0x41a8c[30:29] 0x3
17 0x41a90[28:27] 0x3
18 0x41a94[30:29] 0x1
19 0x41a98[30:29] 0x1
0x41a98[28:27] 0x3
20 0x41a9c[13:12] 0x1
0x41a9c[27:26] 0x1
0x41a9c[17:16] 0x3
0x41a9c[31:30] 0x3
0x41a9c[3:2] 0x3
0x41a9c[15:14] 0x3
0x41a9c[29:28] 0x3
0x41a9c[1:0] 0x3
21 0x41aa4[29:22] 0xf9
0x41aa4[21:14] 0xf9
22 0x41c10[11:8] 0x0
0x41c10[15:12] 0x0
0x41c10[19:16] 0x1
0x41c10[31:28] 0x4
0x41c10[23:20] 0x6
0x41c10[27:24] 0x6
23 0x41c14[7:4] 0x2
0x41c14[19:16] 0x2
0x41c14[3:0] 0x3
0x41c14[15:12] 0x3
0x41c14[11:8] 0x4
0x41c14[23:20] 0x5
0x41c14[27:24] 0x5
24 0x41c64[15:8] 0xf9
0x41c64[20:19] 0x1
0x41c64[24:23] 0x1
0x41c64[22:21] 0x3
0x41c64[28:27] 0x3
0x41c64[26:25] 0x3

Example Tcl scripts for Register Definition, Cache, Calibration to Enable SILB, and Revert to Disable SILB are provided below.

Register Definition:

proc register_def {} {
set ::address0 0x41450
set ::address1 0x41584
set ::address2 0x415dc
set ::address3 0x41674
set ::address4 0x4167c  
set ::address5 0x41680  
set ::address6 0x41684  
set ::address7 0x41758  
set ::address8 0x4175c  
set ::address9 0x41808  
set ::address10 0x41938  
set ::address11 0x4193c  
set ::address12 0x41960  
set ::address13 0x419b4  
set ::address14 0x419b8  
set ::address15 0x41A88  
set ::address16 0x41A8C  
set ::address17 0x41A90  
set ::address18 0x41A94  
set ::address19 0x41A98  
set ::address20 0x41A9C  
set ::address21 0x41AA4  
set ::address22 0x41C10  
set ::address23 0x41C14  
set ::address24 0x41C64
}

Cache:

proc cache {} {
	set ::data0 [master_read_32 $::m $::address0 1]
	set ::data1 [master_read_32 $::m $::address1 1]
	set ::data2 [master_read_32 $::m $::address2 1]
	set ::data3 [master_read_32 $::m $::address3 1]
	set ::data4 [master_read_32 $::m $::address4 1]
	set ::data5 [master_read_32 $::m $::address5 1]
	set ::data6 [master_read_32 $::m $::address6 1]
	set ::data7 [master_read_32 $::m $::address7 1]
	set ::data8 [master_read_32 $::m $::address8 1]
	set ::data9 [master_read_32 $::m $::address9 1]
	set ::data10 [master_read_32 $::m $::address10 1]
	set ::data11 [master_read_32 $::m $::address11 1]
	set ::data12 [master_read_32 $::m $::address12 1]
	set ::data13 [master_read_32 $::m $::address13 1]
	set ::data14 [master_read_32 $::m $::address14 1]
	set ::data15 [master_read_32 $::m $::address15 1]
	set ::data16 [master_read_32 $::m $::address16 1]
	set ::data17 [master_read_32 $::m $::address17 1]
	set ::data18 [master_read_32 $::m $::address18 1]
	set ::data19 [master_read_32 $::m $::address19 1]
	set ::data20 [master_read_32 $::m $::address20 1]
	set ::data21 [master_read_32 $::m $::address21 1]
	set ::data22 [master_read_32 $::m $::address22 1]
	set ::data23 [master_read_32 $::m $::address23 1]
	set ::data24 [master_read_32 $::m $::address24 1]
}

Calibration to Enable SILB:

proc enable_silb {} {
# For 0x41450, OR with 0x40000 to set bit [18] to 0x1.
master_write_32 $::m $::address0 [expr $::data0 | 0x40000]

# For 0x41584, OR with 0x4000, AND with ~(0x8000) to set bits [15:14] to 0x1.
master_write_32 $::m $::address1 [expr [expr $::data1 | 0x4000] &
0xFFFF7FFF]

# For 0x415dc, AND with ~(0x30000000) to set bits [29:28] to 0x0.
master_write_32 $::m $::address2 [expr $::data2 & 0xCFFFFFFF]

# For 0x41674, AND with ~(0x78000000) to set bits [30:27] to 0x0.
master_write_32 $::m $::address3 [expr $::data3 & 0x87FFFFFF]

# For 0x4167c, OR with 0x3C00000 to set bits [23:22] & [25:24] to 0x3.
master_write_32 $::m $::address4 [expr $::data4 | 0x3C00000]

# For 0x41680, AND with ~(0xC0000000) to set bits [31:30] to 0x0.
master_write_32 $::m $::address5 [expr $::data5 & 0x3FFFFFFF]

# For 0x41684, AND with ~(0xD8000000) to set bits [28:27] & [31:30] to 0x0.
master_write_32 $::m $::address6 [expr $::data6 & 0x27FFFFFF]

# For 0x41758, OR with 0x60000000 to set bits [30:29] to 0x3.
master_write_32 $::m $::address7 [expr $::data7 | 0x60000000]

# For 0x4175c, OR with 0x3C000 to set bits [17:14] to 0xF.
master_write_32 $::m $::address8 [expr $::data8 | 0x0003C000]

# For 0x41808, OR with 0x10000, AND with ~(0x8000) to set bits [16:15] to 0x2.
master_write_32 $::m $::address9 [expr [expr $::data9 | 0x10000] &
0xFFFF7FFF]

# For 0x41938, set bits [3:2, 9:8, 11:10, 13:12, 15:14] to 0x1 and bits
[19:18, 25:24, 27:26, 29:28, 31:30] to 0x3.
# OR with 0xff0c5504 to set bits [2, 8, 10, 12, 14] to 0x1 and bits
[19:18, 25:24, 27:26, 29:28, 31:30] to 0x3.
# AND with ~(0xaa08) to set bits [3, 9, 11, 13, 15] to 0x0
master_write_32 $::m $::address10 [expr [expr $::data10 | 0xff0c5504] &
0xFFFF55F7]

# For 0x4193c, OR with 0xFF to set bits [3:0] and [7:4] to 0xF.
master_write_32 $::m $::address11 [expr $::data11 | 0xFF]

# For 0x41960, OR with 0x20000000 to set bit [29] to 0x1.
master_write_32 $::m $::address12 [expr $::data12 | 0x20000000]

# For 0x419b4, OR with 0x10000000 to set bit [28] to 0x1.
master_write_32 $::m $::address13 [expr $::data13 | 0x10000000]

# For 0x419b8, OR with 0x8000000 to set bit [27] to 0x1.
master_write_32 $::m $::address14 [expr $::data14 | 0x8000000]

# For 0x41A88, OR with 0x68000000, AND with ~(0x10000000) to set bits [28:27]
to 0x1 and [30:29] to 0x3.
master_write_32 $::m $::address15 [expr [expr $::data15 | 0x68000000] &
0xEFFFFFFF]

# For 0x41A8C, OR with 0x68000000, AND with ~(0x10000000) to set bits [28:27]
to 0x1 and [30:29] to 0x3.
master_write_32 $::m $::address16 [expr [expr $::data16 | 0x68000000] &
0xEFFFFFFF]

# For 0x41A90, OR with 0x18000000 to set bits [28:27] to 0x3.
master_write_32 $::m $::address17 [expr $::data17 | 0x18000000]

# For 0x41A94, OR with 0x20000000, AND with ~(0x40000000) to set bits [30:29]
to 0x1.
master_write_32 $::m $::address18 [expr [expr $::data18 | 0x20000000] &
0xBFFFFFFF]

# For 0x41A98, OR with 0x38000000, AND with ~(0x40000000) to set bits [30:29]
to 0x1 and bit [28:27] to 0x3.
master_write_32 $::m $::address19 [expr [expr $::data19 | 0x38000000] &
0xBFFFFFFF]

# For 0x41A9C, set bits [13:12, 27:26] to 0x1 and bits [1:0, 3:2, 15:14,
17:16, 29:28, 31:30] to 0x3.
# OR with 0xF403D00F to set bits [12, 26] to 0x1 and bits [1:0, 3:2,
15:14, 17:16, 29:28, 31:30] to 0x3.
# AND with ~(0x8002000) to set bits [13, 27] to 0x0
master_write_32 $::m $::address20 [expr [expr $::data20 | 0xF403D00F] &
0xF7FFDFFF]

# For 0x41AA4, set bits [21:14] and [29:22] to 0xF9.
# OR with 0x3e7e4000, to set bits [14, 17, 18, 19, 20, 21, 22, 25,
26, 27, 28, 29] to 1
# AND with ~(0x1818000) to set bits [15, 16, 23, 24] to 0
master_write_32 $::m $::address21 [expr [expr $::data21 | 0x3e7e4000] &
0xFE7E7FFF]

# For 0x41C10, to set bits [11:8] and [15:12] to 0x0, bit [19:16] to 0x1, bits
[23:20] and [27:24] to 0x6, and bits [31:28] to 0x4.
# OR with 0x46610000 to set bits [16, 21, 22, 25, 26, 30] to 0x1
# AND with ~(0xB99EFF00) to set bits [11:8, 15:12, 19:17, 20, 23, 24,
27, 29:28, 31] to 0x0
master_write_32 $::m $::address22 [expr [expr $::data22 | 0x46610000] &
0x466100FF]

# For 0x41C14, to set bit [3:0] to 0x3, bits [7:4] to 0x2, bits [11:8] to 0x4,
bits [15:12] to 0x3, bits [19:16] to 0x2, bits [23:20] and [27:24] to 0x5.
# OR with 0x5523423 to set bits [0, 1, 5, 10, 12, 13, 17, 20, 22, 24,
26] to 0x1
# AND with ~(0xAADCBDC) to set bits [2, 3, 4, 6, 7, 8, 9, 11, 14, 15,
16, 18, 19, 21, 23, 25, 27] to 0x0
master_write_32 $::m $::address23 [expr [expr $::data23 | 0x5523423] &
0xF5523423]

# For 0x41C64, to set bits [15:8] to 0xF9 and set bits [20:19], [24:23] to 0x1
and bits [22:21], [26:25], [28:27] to 0x3.
# OR with 0x1ee8f900 to set bits [8, 11, 12, 13, 14, 15, 19, 21, 22,
23, 25, 26, 27, 28] to 0x1
# AND with ~(0x1100600) to set bits [9, 10, 20, 24] to 0x0
master_write_32 $::m $::address24 [expr [expr $::data24 | 0x1ee8f900] &
0xFEEFF9FF]
}

Revert to Disable SILB:

proc disable_silb {} {
master_write_32 $::m $::address0 $::data0
	master_write_32 $::m $::address1 $::data1
	master_write_32 $::m $::address2 $::data2
	master_write_32 $::m $::address3 $::data3
	master_write_32 $::m $::address4 $::data4
	master_write_32 $::m $::address5 $::data5
	master_write_32 $::m $::address6 $::data6
	master_write_32 $::m $::address7 $::data7
	master_write_32 $::m $::address8 $::data8
	master_write_32 $::m $::address9 $::data9
	master_write_32 $::m $::address10 $::data10
	master_write_32 $::m $::address11 $::data11
	master_write_32 $::m $::address12 $::data12
	master_write_32 $::m $::address13 $::data13
	master_write_32 $::m $::address14 $::data14
	master_write_32 $::m $::address15 $::data15
	master_write_32 $::m $::address16 $::data16
	master_write_32 $::m $::address17 $::data17
	master_write_32 $::m $::address18 $::data18
	master_write_32 $::m $::address19 $::data19
	master_write_32 $::m $::address20 $::data20
	master_write_32 $::m $::address21 $::data21
	master_write_32 $::m $::address22 $::data22
	master_write_32 $::m $::address23 $::data23
	master_write_32 $::m $::address24 $::data24
}
Level Two Title