Visible to Intel only — GUID: nch1711586076357
Ixiasoft
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters for E-Series FPGA
6. IP Parameters for D-Series FPGAs
7. Interfaces and Signals
8. Registers
9. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
3.1. Downloading and Installing Quartus® Prime Software
3.2. Configuring and Generating the GTS AXI Streaming IP
3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP
3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP
3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs)
3.6. Simulating the GTS AXI Streaming IP Variant
3.7. Compiling the GTS AXI Streaming IP Variant
4.1. Clocking
4.2. Resets
4.3. PCIe* Hard IP
4.4. Hard IP Interface (IF) Adaptor
4.5. Interrupts
4.6. Transaction Ordering
4.7. TX Non-Posted Metering Requirement on Application
4.8. AXI4-Stream Interface
4.9. Tag Allocation
4.10. Precision Time Measurement (PTM)
4.11. Single Root I/O Virtualization (SR-IOV)
4.12. Transaction Layer Packet (TLP) Bypass Mode
4.13. Scalable IOV
7.1. Overview
7.2. Clocks and Resets
7.3. AXI4-Stream Interfaces
7.4. Configuration Intercept Interface
7.5. Control Shadow Interface
7.6. Transmit Flow Control Credit Interface
7.7. Completion Timeout Interface
7.8. Control and Status Register Responder Interface
7.9. Function Level Reset Interface
7.10. TLP Bypass Error Reporting Interface
7.11. VF Error Flag Interface
7.12. Precision Time Measurement (PTM) Interface
7.13. Serial Data Signals
7.14. Miscellaneous Signals
8.6.1. VF PCI-Compatible Configuration Space Header Type0
8.6.2. VF PCI Express* Capability Structure
8.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure
8.6.4. VF Alternative Routing ID (ARI) Capability Structure
8.6.5. VF TLP Processing Hints (TPH) Capability Structure
8.6.6. VF Address Translation Services (ATS) Capability Structure
8.6.7. VF Access Control Services (ACS) Capability Structure
8.6.2.1. PCI Express* Capability List Register
8.6.2.2. PCI Express* Device Capabilities Register
8.6.2.3. PCI Express* Device Control and Status Register
8.6.2.4. Link Capabilities Register
8.6.2.5. Link Control and Status Register
8.6.2.6. PCI Express* Device Capabilities 2 Register
8.6.2.7. PCI Express* Device Control and Status 2 Register
8.6.2.8. Link Capabilities 2 Register
8.6.2.9. Link Control and Status 2 Register
Visible to Intel only — GUID: nch1711586076357
Ixiasoft
A.2.4.3.2. TX Path
This tab allows you to monitor the transmitter settings for the channel selected.
Parameters | Values | Descriptions | |
---|---|---|---|
TX Status | TX Electrical Idle | True, False | Indicates if TX is in electrical idle.
|
TX PLL | TX PLL lock | Green, Red | Indicates if TX PLL is locked.
|
TX Equalization | TX Equalization Status | Not attempted, Completed, Unsuccessful | Indicates transmitter equalization status. The TX local and remote parameters are valid only when the value of Equalization status is returned as completed, indicating equalization has completed successfully. |
TX Local Preset | P0 to P10 | Indicates the transmitter driver preset value as requested by the link partner during the Equalization phase of link training. If the preset is not one of these values, then no value is shown. | |
Local Pre-shoot coefficient | Depends on the coefficient requested by the link partner. | Indicates the transmitter driver output pre-emphasis (pre-cursor coefficient value). | |
Local main coefficient | Depends on the coefficient requested by the link partner. | Indicates the transmitter driver output pre-emphasis (main cursor coefficient value). | |
Local post coefficient | Depends on the coefficient requested by the link partner. | Indicates the transmitter driver output pre-emphasis (post-cursor coefficient value). | |
Remote Pre-shoot coefficient 5 | Depends on the transmitter driver output of the link partner. | Indicates link partner's transmitter driver's output pre-cursor coefficient value, as received by Agilex™ 5 during the Equalization phase of link training. When Agilex™ 5 is configured in Endpoint mode, this value corresponds to the coefficient received during Phase 2 of Equalization. | |
Remote main coefficient5 | Depends on the transmitter driver output of the link partner. | Indicates link partner's transmitter driver's output main cursor coefficient value, as received by Agilex™ 5 during the Equalization phase of link training. When Agilex™ 5 is configured in Endpoint mode, this value corresponds to the coefficient received during Phase 2 of Equalization. | |
Remote post coefficient5 | Depends on the transmitter driver output of the link partner. | Indicates the link partner's transmitter driver's output post-cursor coefficient value, as received by Agilex™ 5 during the Equalization phase of link training. When Agilex™ 5 is configured in Endpoint mode, this value corresponds to the coefficient received during Phase 2 of Equalization. | |
Remote full swing (fs)5 | Depends on the device capability of the link partner. | Indicates the full swing value used by the link partner during the Equalization phase of link training. | |
Remote low frequency (lf)5 | Depends on the device capability of the link partner. | Indicates the low frequency value used by the link partner during the Equalization phase of link training. |
Figure 78. Example of Transmitter Settings
5 Refer to the following sections of the PCI Express* Base Specification Revision 4.0: 4.2.3 Link Equalization Procedure for 8.0 GT/s and Higher Data Rates and 8.3.3 Tx Voltage Parameters.