GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

4.7. TX Non-Posted Metering Requirement on Application

PCI Express* HIP implements a finite number of RX Completion Buffers for its header and data. However, in endpoint mode, it advertises infinite credit to the host. Hence,, the application logic needs to implement metering logic on its TX Non-Posted requests such that it does not issue more requests than allowed to avoid overflowing the completion buffer.

Table 15.  Completion Buffer SizeThe receive buffer instantiates separate memories for header and data.
Completion Buffer Depth Width (in bits)
Port 0 Completion Header 286 128
Port 0 Completion Data 1730 64
Table 16.  Credit Advertised by GTS AXI Streaming IP
RX Buffer Segment x4 Controller
Scaled Flow Control Disabled (Credit) Scaled Flow Control Enabled (Scale Factor, Credit)
Posted Headers 127 2, 56
Posted Data 444 1, 444
Non-posted Headers 127 2, 56
Non-posted Data 112 1, 112