GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

4.2. Resets

The GTS AXI Streaming IP has two types of resets:

  • Bus Resets—The bus resets are AXI specification defined reset signals, that is used to reset the logic in the GTS AXI Streaming IP interfacing with AXI fabric.
  • IP Resets—The IP reset signals perform cold/warm reset sequences.
The GTS AXI Streaming IP has the following reset domains to drive the various interfaces.
Table 10.  Reset Domains in the GTS AXI Streaming IP
Reset Domain Type Description
Cold reset IP reset

A Fundamental Reset following the application of main power.

Initiated by the deassertion of pin_perst_n signal. This resets the following:
  • Bus resets (AXI-Stream/AXI-Lite)
  • Hard IP
  • Sticky registers of configuration space

When cold reset is triggered, warm reset and bus resets must be asserted.

Refer to PCI Express* Base Specification Revision 4.0 for more details on cold reset.

Warm reset IP reset
A Fundamental Reset without cycling main power. This resets the following:
  • Bus resets (AXI-Stream/AXI-Lite)
  • Hard IP

The warm reset can be triggered multiple times by user without going through cold reset sequence. When warm reset is triggered, Bus resets must be asserted.

Refer to the PCI Express* Base Specification Revision 4.0 for more details on warm reset.

AXI-Stream reset Bus reset This resets the AXI-Stream main data path interface (e.g., AXI-Stream TX/RX).
AXI-Lite reset Bus reset This resets the AXI4-Lite Control and Status Register Responder interface (e.g., Completion timeout, control and status register).

For each GTS bank, there are two pins in HVIO banks with optional function as platform PCIe* reset (PERST#) for the PCIe* link in the bank. You can connect PERST# to either one of the reset pins. Assign pin_perst input port of the GTS AXI Streaming IP to the location of the reset pin connected to PERST#. For the reset pin not used for PERST#, it can be used as a generic HVIO signal. For example, if the PIN_PERST_N_CVP_L1A_0 pin in Bank 5A is connected to PERST# for the PCIe* link in Bank L1A, the PIN_PERST_N_CVP_L1A_1 pin in Bank 5B can be used as a generic HVIO signal. Resetting a PCIe* link in one bank does not affect the PCIe* links in other banks.

For a description of the dual-purpose pins in the HVIO banks function as PCIe* platform reset, refer to the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs .
Note: For Agilex™ 5 ES E-Series devices in the current Quartus® Prime software release, you must assign both p0_pin_perst_n_i and p0_pin_perst_n_1_i ports to the location of the reset pins in HVIO banks as shown in the following table. Connect PERST# to either one of the reset pins. For the other reset pin that is not used as PERST#, it must be left floating at board level. For example, for a PCIe* link in GTS bank L1A, assign p0_pin_perst_n_i to pin PIN_PERST_N_CVP_L1A_0 and assign p0_pin_perst_n_1_i to pin PIN_PERST_N_CVP_L1A_1. If you connect PERST# to PIN_PERST_N_CVP_L1A_0, leave PIN_PERST_N_CVP_L1A_1 floating at board level. Tie the i_gpio_perst0_n port to logic high.
Table 11.  Pin Location Assignment for p0_pin_perst_n_i and p0_pin_perst_n_1_i Ports
PCIe* Link in GTS Bank HVIO Reset Pins Driving pin_perst Port
p0_pin_perst_n_i p0_pin_perst_n_i
Bank L1A PIN_PERST_N_CVP_L1A_0 PIN_PERST_N_CVP_L1A_1
Bank L1B PIN_PERST_N_CVP_L1B_0 PIN_PERST_N_CVP_L1B_1
Bank L1C PIN_PERST_N_CVP_L1C_0 PIN_PERST_N_CVP_L1C_1
Bank R4A PIN_PERST_N_R4A_1 PIN_PERST_N_R4A_0
Bank R4B PIN_PERST_N_R4B_1 PIN_PERST_N_R4B_0
Bank R4C PIN_PERST_N_R4C_1 PIN_PERST_N_R4C_0

Avoid triggering pin_perst_n during a Functional Level Reset or before a Functional Level Reset completion. The minimum interval requirement between two consecutive reset is 500 μs. It is applicable to PERST# and hot reset. In the other words, the minimum interval time required between the deassertion of the PERST# to the assertion of the next PERST# is 500 μs.

Figure 11. Reset Domains