GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

7.1. Overview

The number of IP-to-User Logic interfaces exposed to the FPGA fabric are different based on the configuration modes.

Note: Only the supported interfaces in this release are shown in the following figure.
Figure 43.  GTS AXI Streaming IP—Top-Level Signals

The following table shows the variables that are used to define the bus indices for top level signal buses shown in the figure above. The values of these variables change depending on the configuration used.

Table 36.  Variables Used in the Bus Indices
Variable PCIe* 4.0 x8 PCIe* 4.0 x4 PCIe* 3.0 x8 PCIe* 3.0 x4 PCIe* 4.0 x2/ PCIe* 3.0 x2 PCIe* 4.0 x1/ PCIe* 3.0 x1
a 512 256 256 128
b 8 4 8 4 2 1