Visible to Intel only — GUID: udp1711161034500
Ixiasoft
Visible to Intel only — GUID: udp1711161034500
Ixiasoft
A.2.1. Overview
The Agilex™ 5 Debug Toolkit is a System Console-based tool that provides real-time control, monitoring and debugging of the PCIe* links at the Physical Layer.
The Agilex™ 5 Debug Toolkit allows you to:
- View protocol and link status of the PCIe* links.
- View PLL and per-channel status of the PCIe* links.
- View the channel analog settings.
- Indicate the presence of a re-timer connected between the link partners.
The following figure provides an overview of the Agilex™ 5 Debug Toolkit in the GTS AXI Streaming IP.
When you enable the Agilex™ 5 Debug Toolkit, the GTS AXI Streaming IP module of the generated IP includes the Debug Toolkit modules and related logic as shown in the figure above.
Drive the Debug Toolkit from System Console. The System Console connects to the Debug Toolkit via the Native PHY Debug Master Endpoint (NPDME). Make this connection via an Intel® FPGA Download Cable.
When the Debug Toolkit is enabled, a multiplexer is implemented to allow switching between the Control and Status Register Responder Interface and the System Console-based Debug Toolkit. This allows you to switch between the user logic driving the Control and Status Register Responder Interface and the Debug Toolkit, as both access the same set of registers within the Hard IP.
The Debug Toolkit is launched successfully only if pending read/write transactions on the Control and Status Register Responder Interface are completed (as indicated by the deassertion of the reconfig_waitrequest signal).
Provide a clock source (100 MHz–250 MHz) to drive the axi_lite_clk clock. Use the output of the Reset Release Intel® FPGA IP to drive the ninit_done, which provides the reset signal to the NPDME module.