GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

2.2. IP Support Status

The feature of GTS AXI Streaming IP outlined above is enabled gradually in the subsequent Quartus® Prime Pro Edition software releases. The following table shows the IP support status in the current release.

Table 2.  Feature Support Status
Feature Support Status
GTS AXI Streaming IP
  • Supported configurations:
    • PCIe* 4.0 x8 Endpoint/Root Port 512-bit AXI-Stream data bus width
    • PCIe* 4.0 x4 Endpoint/Root Port 256-bit AXI-Stream data bus width
    • PCIe 3.0 x8 Endpoint/Root Port 256-bit AXI-Stream data bus width
    • PCIe* 3.0 x4 Endpoint/Root Port 128-bit AXI-Stream data bus width
    • PCIe* 4.0 x2 Endpoint/Root Port 128-bit AXI-Stream data bus width
    • PCIe* 3.0 x2 Endpoint/Root Port 128-bit AXI-Stream data bus width
    • PCIe* 4.0 x1 Endpoint/Root Port 128-bit AXI-Stream data bus width
    • PCIe* 3.0 x1 Endpoint/Root Port 128-bit AXI-Stream data bus width
    • PCIe 4.0 x8 TLP BypassTLP-Bypass (Upstream/Downstream Port) 512-bit AXI-Stream data bus width
    • PCIe* 4.0 x4 TLP BypassTLP-Bypass (Upstream/Downstream Port) 256-bit AXI-Stream data bus width
    • PCIe 3.0 x8 TLP BypassTLP-Bypass (Upstream/Downstream Port) 256-bit AXI-Stream data bus width
    • PCIe* 3.0 x4 TLP Bypass Upstream/Downstream Port) 128-bit AXI-Stream data bus width
    • PCIe* 4.0 x2 TLP Bypass (Upstream/Downstream Port) 128-bit AXI-Stream data bus width
    • PCIe* 3.0 x2 TLP Bypass (Upstream/Downstream Port) 128-bit AXI-Stream data bus width
    • PCIe* 4.0 x1 TLP Bypass (Upstream/Downstream Port) 128-bit AXI-Stream data bus width
    • PCIe* 3.0 x1 TLP Bypass (Upstream/Downstream Port) 128-bit AXI-Stream data bus width
Note: PCIe* 1.0/ PCIe* 2.0 speed are supported through link down-training.
Note: PCIe* x8 link width is only supported in Agilex™ 5 D-Series FPGAs.
  • Supported features:
    • Legacy Interrupt, MSI, and MSI-X
    • Separate Refclk with no Spread Spectrum Clocking (SRNS)
    • Separate Refclk with Independent Spread Spectrum Clocking (SRIS)
    • Atomic Operation
    • Supports up to 512-byte maximum payload size (MPS)
    • Supports up to 2 KB maximum read request size (MRRS), 4KB option can only be supported in the production silicon.
    • Advanced Error Reporting
    • Single Root I/O Virtualization (SR-IOV)
    • Scalable I/O
    • PTM
    • Lane reversal
    • Configuration Intercept Interface
    • Debug Toolkit
Quartus® Prime Pro Edition Support
  • Compilation, Simulation, and Timing
  • IP Catalog "standalone" generation
  • SDC generation
Simulation
  • VCS* MX, QuestaSim* , Xcelium* , and Riviera-PRO*
  • FASTSIM and PIPE mode simulation
Hardware Limited hardware support
Design Example PCIe* 4.0 x4 256-bit PIO Design Example

Standards and Specifications Compliance

Table 3.   GTS AXI Streaming IP Standards and Specifications Revision/Version
Standard Revision/Version
PCI Express* Base Specification 4.0
PHY Interface for PCI Express* Architecture 4.4.1
Single Root I/O Virtualization and Sharing Specification 1.1
Address Translation Services 1.1
Virtual I/O Device (VirtIO) 1.0
AMBA Stream Protocol Specification AXI-4