GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

4.3. PCIe* Hard IP

The PCIe* Hard IP implements the functionality of the PCIe* protocol. The Hard IP implements Physical, Data Link, and Transaction Layers of the protocol. The Hard IP handles link training, DLLP exchanges, credit handling, BAR decode, and error handling in normal mode. It also implements SR-IOV functionality for virtualization applications.

The Agilex™ 5 FPGAs and SoCs provide two variants of the PCIe* Hard IP: PCIe* 4.0 x8 Hard IP for the performance-optimized D-Series FPGAs and PCIe* 4.0 x4 Hard IP for the power-optimized E-Series FPGAs. In the E-Series devices, the PCIe* 4.0 x4 Hard IP consists of a PCIe* x4 controller and is available in every transceiver bank. While in the D-Series devices, the PCIe* 4.0 x8 Hard IP spans two transceiver banks and consists of a PCIe* x8 controller and a PCIe* x4 controller. The PCIe* x8 controller can also support a x4 link and hence the PCIe* 4.0 x8 Hard IP in the D-Series devices can be configured to support two independent PCIe* x4 links. There are reference clock pins and a System PLL in each transceiver bank, and reset pins in the HVIO banks to enable independent PCIe* links. When the PCIe* Hard IP is configured to support PCIe* 4.0 x8 mode with two transceiver banks combined, only the PCIe* x8 controller and the System PLL in the upper bank are active.

Figure 12.  Agilex™ 5 PCIe* 4.0 x4 Hard IP Block Diagram for E-Series FPGAs
Figure 13.  Agilex™ 5 PCIe* 4.0 x8 Hard IP Block Diagram for D-Series FPGAs