GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

7.5. Control Shadow Interface

The control shadow interface brings out the settings of the various configuration register fields of the function. These fields are mandatory to design the control path of the application layer logic.

The application logic decodes information provided on this interface to create a shadow copy. The interface provides update to primary control signals only. The application logic must read extra information required through the AXI4-Lite Control and Status Register Responder interface by reading configuration register of interest.

Table 45.  Control Shadow Interface—Available Settings of Various Configuration Register Fields
Function Description
Bus Master Enable
  • The application logic requires the BME information to determine if it can generate request for a particular function.
  • Each function in the application logic cannot generate bus master requests unless its corresponding BME is set.
  • The application logic monitors control shadow interface for BME event for this purpose.
  • Since the GTS AXI Streaming IP does not autonomously generate bus master request by itself, it does not qualify the transmit path with BME settings and solely relies on application.
MSI-X Mask
  • It is the Function Mask bit, indicate that all of the vectors associated with the Function are masked when set, regardless of their per-vector Mask bit values.
  • Each vector's Mask bit determines whether the vector is masked or not when this bit is clear.
MSI-X Enable
  • The application logic requires MSI-X Address and MSI-X Data information from MSI-X capability to generate the MSI-X interrupt.
  • The application logic monitors control shadow interface for MSI-X Enable event to read these additional information from MSI-X capability.
MemSpace Enable
  • It controls a Function's response to Memory Space accesses.
  • When this bit is Clear, all received Memory Space accesses are caused to be handled as Unsupported Requests.
  • When this bit is set, the Function is enabled to decode the address and further process Memory Space accesses.
  • For a Function with a Type 1 Configuration Space header, this bit controls the response to the Memory Space accesses received on its Primary Side.
ExpRom Enable It indicates whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b, the Function's expansion ROM address space is disabled. When the bit is 1b, the address decoding is enabled using the parameters in the other part of the Expansion ROM Base Address register.
TPH Req Enable
  • The function supports all operational modes of TPH, no ST mode, interrupt vector mode or device specific mode.
  • The HOST communicates mode of operation by writing ST Mode Select bits in TPH requester control register.
  • The application reads this register and generates traffic only when TPH requester enable bit is set.
ATS Enable
  • The function can read Smallest Translation Unit (STU) field from ATS control register when ATS enable bit is set.
  • The following figure shows output on the Control Shadow interface when there is an update to the control shadow bits in the HIP configuration register.
MSI Enable
  • The application logic requires MSI Address and MSI Data information from MSI capability to generate MSI interrupt.
  • The application logic monitors control shadow interface for MSI Enable event to read this additional information from MSI capability.
MSI Mask It indicates the Function supports MSI Per-Vector Masking when set and not supported when clear.
Extended Tag It indicates 8-bit Tag field generation is enabled when set and 5-bit Tag field generation when clear.
10bit Tag Req Enable It indicates that the Requester is permitted to use 10-Bit Tags when set, not permitted when clear.
PTM Enable It indicates that a Function is permitted to participate in the PTM mechanism according to its selected roles when set and not permitted when it is cleared.
Maximum Payload Size (MPS)
The defined encodings are:
  • 000b: 128 bytes max payload size
  • 001b: 256 bytes max payload size
  • 010b: 512 bytes max payload size
  • 011b: 1024 bytes max payload size
  • 100b: 2048 bytes max payload size
  • 101b: 4096 bytes max payload size
  • 110b: Reserved
  • 111b: Reserved
Maximum Read Request Size (MRRS)
The defined encodings are:
  • 000b: 128 bytes maximum Read Request size
  • 001b: 256 bytes maximum Read Request size
  • 010b: 512 bytes maximum Read Request size
  • 011b: 1024 bytes maximum Read Request size
  • 100b: 2048 bytes maximum Read Request size
  • 101b: 4096 bytes maximum Read Request size
  • 110b: Reserved
  • 111b: Reserved
Virtual Function (VF) Enable
  • The Virtual Function in application logic cannot generate any traffic unless they are enabled by HOST. The number of VFs enabled can be different than the number of VFs advertised as initial VFs.
  • The application logic can find the number of VFs visible by reading the NumVFs register in the SR-IOV capability.
  • The read of this register must be triggered after the VF Enable bit is set by HOST.
  • It indicates that VFs associated with PF are accessible in the PCI Express* fabric when set.
  • VFs are disabled and not visible in the PCI Express* fabric when clear.
Page Request Enable It indicates that the Page Request Interface is allowed to make page requests when set, not allowed when clear.
Figure 56. Control Shadow Interface Timing Diagram During an Update
Table 46.  Control Shadow Interface Signalsn = 0 or 1, p0 = port 0, and p1 = port 1
Note: Port 1 is only available in D-Series FPGAs
Signal Name Direction Clock Domain Description
p<n>_ss_app_st_ctrlshadow_tvalid Output p<n>_axi_lite_clk

The GTS AXI Streaming IP asserts this output for one clock cycle when there is an update to the register fields being monitored, because of a Configuration Write performed by the root complex.

You can copy the new settings of the register fields from the p<n>_ss_app_st_ctrlshadow_tdata[39:0] bus.

p<n>_ss_app_st_ctrlshadow_tdata[39:0] Output p<n>_axi_lite_clk

When p<n>_ss_app_st_ctrlshadow_tvalid has been asserted, this output provides the current settings of the register fields of the associated Function.

  • Bit [2:0]: Identifies the physical function number of configuration register.
  • Bit [13:3]: Identifies the virtual function number of configuration register.
  • Bit [14]: Indicates information is for virtual function implemented in slot's physical function.
  • Bit [19:15]: Identifies the slot number of configuration register.
  • Bit [20]: Bus Master Enable
  • Bit [21]: MSI-X Mask
  • Bit [22]: MSI-X Enable
  • Bit [23]: MemSpace Enable
  • Bit [24]: ExpRom Enable
  • Bit [25]: TPH Req Enable
  • Bit [26]: ATS Enable
  • Bit [27]: MSI Enable
  • Bit [28]: MSI Mask
  • Bit [29]: Extended Tag
  • Bit [30]: 10Bit Tag Req Enable
  • Bit [31]: PTM Enable
  • Bit [34:32]: MPS
  • Bit [37:35]: MRRS
  • Bit [38]: VF Enable
  • Bit [39]: Page Request Enable