GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

7.7. Completion Timeout Interface

The completion timeout interface indicates completion timeout event to application. The interface provides the function number and tag number of the outstanding request timed out.

Table 48.  Completion Timeout Interfacen = 0 or 1, p0 = port 0, and p1 = port 1
Note: Port 1 is only available in D-Series FPGAs
Signal Name Direction Clock Domain Description
p<n>_ss_app_st_cplto_tvalid Output p<n>_axi_lite_clk

p<n>_ss_app_st_cplto_tvalid indicates that the completion timeout received for an outstanding non-posted request.

p<n>_ss_app_st_cplto_tdata[29:0] Output p<n>_axi_lite_clk

Carries completion timeout information.

Bit [9:0]: Tag number.

Bit [12:10]: PF number, indicates parent PF number of VF when VF active is high else PF number of function.

Bit [23:13]: VF number, indicates VF number when VF active is high.

Bit [24]: VF active, indicates timeout is for VF.

Bit [29:25]: Reserved.