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1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
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1.5. Agilex™ 5 Ethernet Hard IP Features
The GTS Ethernet Intel® FPGA Hard IP supports the following features listed in the table:
Features | Description |
---|---|
Ethernet Rate/PMA combination [Data rate]- [Number of PMAs] |
|
PMA type | GTS: ETH MAC and OTN support on CH3 and CH2 2 per bank. All channels support PCS Direct and FlexE mode. |
Flexible Configuration |
|
Client interface |
|
Forward Error Correction (FEC) |
|
Precision Timing and Link Training |
|
Ethernet Mode | Modulation | FEC Selection | MAC AVST | PCS (MII) | PCS (OTN/ FlexE) | PTP 1588v2 | AN/LT | ||
---|---|---|---|---|---|---|---|---|---|
No FEC | CL74 | CL911 | |||||||
10GE-1 | NRZ | Y | Y | N/A | Y | Y | Y | Y | Y |
25GE-11 | NRZ | Y | Y | Y | Y | Y | Y | Y | Y |
Ethernet Mode | Protocol | Number of Channels and Line Rate |
---|---|---|
10GE-1 | 10GBASE-KR | 1x10.3125 Gbps NRZ channel for Copper Backplane |
25GE-11 | 25GBASE-KR | 1x25.78125 Gbps NRZ channel for Copper Backplane |
25GBASE-CR | 1x25.78125 Gbps NRZ channel for Direct Attach Copper Cable |
1 Feature supported in D-Series and E-Series Device Group A only.
2 CH2 supports MAC only for D-Series devices.
3 This feature requires patch 0.01. You need to download and apply this patch to access the functionality.