GTS Ethernet Intel® FPGA Hard IP User Guide

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ID 817676
Date 10/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Install and License the GTS Ethernet Intel® FPGA Hard IP 3. Configure and Generate Ethernet Hard IP variant 4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application 5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance 6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance 7. Simulate, Compile, and Validate SyncE - Single Instance 8. Simulate and Compile PTP1588 - Single Instance 9. Simulate, Compile, and Validate - Multiple Instance 10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training 11. Troubleshoot and Diagnose Issues A. Appendix A: Functional Description B. Appendix B: Configuration Registers C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Release Information 1.2. High-Level Functional Overview 1.3. Acronyms 1.4. Agilex™ 5 Ethernet Portfolio and Target Applications 1.5. Agilex™ 5 Ethernet Hard IP Features 1.6. GTS Ethernet Intel® FPGA Hard IP Design Flow
1.5. Agilex™ 5 Ethernet Hard IP Features x
1.5.1. Device Family Support 1.5.2. Device Speed Grade Support 1.5.3. Resource Utilization
3. Configure and Generate Ethernet Hard IP variant x
3.1. Create Quartus Project 3.2. Configure GTS Ethernet Hard IP 3.3. Generate HDL for Synthesis and Simulation 3.4. Generated File Structure 3.5. Generate GTS EHIP Design Example 3.6. Analog Parameter Options
3.5. Generate GTS EHIP Design Example x
3.5.1. Directory Structure
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application x
4.1. Implement Required Clocking 4.2. Implement Required Resets 4.3. Connect the Status Interface 4.4. Connect the MAC Avalon Streaming Client Interface 4.5. Connect the MII PCS Only Client Interface 4.6. Connect the PCS66 Client Interface – FlexE and OTN 4.7. Connect the Precision Time Protocol Interface 4.8. Connect the Ethernet Hard IP Reconfiguration Interface 4.9. Connect the Auto-Negotiation and Link Training
4.1. Implement Required Clocking x
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance 4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances 4.1.3. Implement Clock Connections to MAC Asynchronous Operation 4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E) 4.1.5. Implement Clock Connections in PTP-Based Design
4.2. Implement Required Resets x
4.2.1. Reset Sequence 4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP
4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP x
4.2.2.1. Requirements and Considerations for GTS Reset Sequencer Intel® FPGA IP
4.3. Connect the Status Interface x
4.3.1. Use i_stats_snapshot to Read Stats Counters
4.4. Connect the MAC Avalon Streaming Client Interface x
4.4.1. Connect the TX MAC Avalon Streaming Client Interface 4.4.2. Connect the RX MAC Avalon Streaming Client Interface 4.4.3. Connect the MAC Flow Control Interface
4.4.1. Connect the TX MAC Avalon Streaming Client Interface x
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough 4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion 4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2. Connect the RX MAC Avalon Streaming Client Interface x
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled 4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled 4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled 4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.4.3. Connect the MAC Flow Control Interface x
4.4.3.1. Connect the TX MAC Flow Control Interface 4.4.3.2. Connect the RX MAC Flow Control Interface
4.5. Connect the MII PCS Only Client Interface x
4.5.1. Connect the MII PCS Mode TX Interface 4.5.2. Connect the MII PCS Mode RX Interface
4.5.1. Connect the MII PCS Mode TX Interface x
4.5.1.1. Insert Alignment Marker
4.5.2. Connect the MII PCS Mode RX Interface x
4.5.2.1. Receive Alignment Marker
4.6. Connect the PCS66 Client Interface – FlexE and OTN x
4.6.1. Connect the FlexE and OTN Mode TX Interface 4.6.2. Connect the FlexE and OTN Mode RX Interface
4.6.1. Connect the FlexE and OTN Mode TX Interface x
4.6.1.1. Insert Alignment Marker
4.6.2. Connect the FlexE and OTN Mode RX Interface x
4.6.2.1. Receive Alignment Marker
4.7. Connect the Precision Time Protocol Interface x
4.7.1. Connect the Time-of-Day Interface 4.7.2. Connect the TX Two-Step Timestamp Interface 4.7.3. Connect the TX One-Step Timestamp Interface 4.7.4. Connect the RX Timestamp Interface 4.7.5. Connect the PTP Status Interface
4.7.3. Connect the TX One-Step Timestamp Interface x
4.7.3.1. PTP Field Offset for 1-Step Operation
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance x
5.1. Design Example Features 5.2. Design Example Components 5.3. Simulate the Design Example 5.4. Compile the Design Example 5.5. Validate the Design Example
5.3. Simulate the Design Example x
5.3.1. Simulation Testbench Flow 5.3.2. Verify the Simulation Results
5.5. Validate the Design Example x
5.5.1. Configure the Clocks in Hardware 5.5.2. Program the FPGA 5.5.3. Run the Hardware Test
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance x
6.1. Design Example Features 6.2. Design Example Components 6.3. Simulate the Design Example 6.4. Compile the Design Example 6.5. Validate the Design Example
6.3. Simulate the Design Example x
6.3.1. Simulation Testbench Flow 6.3.2. Simulators Output
6.5. Validate the Design Example x
6.5.1. Configure the Clocks in Hardware 6.5.2. Program the FPGA 6.5.3. Run the Hardware Test
7. Simulate, Compile, and Validate SyncE - Single Instance x
7.1. Design Example Features 7.2. Design Example Components 7.3. Simulate the Design Example 7.4. Compile the Design Example 7.5. Validate the Design Example
7.3. Simulate the Design Example x
7.3.1. Simulation Testbench Flow for Single Instance with SyncE 7.3.2. Simulator Output
7.5. Validate the Design Example x
7.5.1. Configure the Clocks in Hardware 7.5.2. Program the FPGA 7.5.3. Run the Hardware Test
8. Simulate and Compile PTP1588 - Single Instance x
8.1. Design Example Features 8.2. Design Example Components 8.3. Simulate the Design Example 8.4. Compile the Design Example 8.5. Validate the Design Example
8.3. Simulate the Design Example x
8.3.1. Simulation Testbench Flow 8.3.2. Simulator Output
8.5. Validate the Design Example x
8.5.1. Configure the Clocks in Hardware 8.5.2. Program the FPGA 8.5.3. Run the Hardware Test
9. Simulate, Compile, and Validate - Multiple Instance x
9.1. Design Example Features 9.2. Design Example Components 9.3. Simulate the Design Example 9.4. Compile the Design Example 9.5. Validate the Design Example
9.3. Simulate the Design Example x
9.3.1. Simulation Testbench Flow for MAC Mode 9.3.2. Simulator Output
9.5. Validate the Design Example x
9.5.1. Configure the Clocks in Hardware 9.5.2. Program the FPGA 9.5.3. Run the Hardware Test
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training x
10.1. Design Example Features 10.2. Design Example Components 10.3. Simulate the Design Example 10.4. Compile the Design Example 10.5. Validate the Design Example
10.3. Simulate the Design Example x
10.3.1. Simulation Testbench Flow 10.3.2. Simulation Output
10.5. Validate the Design Example x
10.5.1. Configure the Clocks in Hardware 10.5.2. Program the FPGA 10.5.3. Run the Hardware Test
11. Troubleshoot and Diagnose Issues x
11.1. Enable Diagnostic Lookback Modes 11.2. Troubleshoot the Reset Sequence 11.3. Use Signal Tap Analyzer for Troubleshooting
11.1. Enable Diagnostic Lookback Modes x
11.1.1. Internal Serial Loopback 11.1.2. Enable MAC Loopback 11.1.3. Enable PCS Loopback 11.1.4. Enable External Loopback 11.1.5. Packet Client Loopback
11.2. Troubleshoot the Reset Sequence x
11.2.1. Debug the Power Up Reset Sequence 11.2.2. Debug the TX Reset Entry Sequence 11.2.3. Debug the TX Reset Exit Sequence 11.2.4. Debug the RX Reset Entry Sequence 11.2.5. Debug the RX Reset Exit Sequence 11.2.6. Debug the Auto Recovery Reset Sequence
A. Appendix A: Functional Description x
A.1. Datapath Description A.2. GTS Ethernet Intel® FPGA Hard IP MAC A.3. PCS, OTN, and FlexE Modes A.4. Precision Time Protocol Interface A.5. Auto-Negotiation and Link Training
A.2. GTS Ethernet Intel® FPGA Hard IP MAC x
A.2.1. MAC TX Datapath A.2.2. MAC RX Datapath A.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) A.2.4. Link Fault Signaling A.2.5. Order of Ethernet Transmission:
A.2.1. MAC TX Datapath x
A.2.1.1. Insert TX Preamble, Start, and SFD A.2.1.2. Insert Source Address A.2.1.3. Process Length/Type Field A.2.1.4. Pad the Client Frame A.2.1.5. Insert Frame Check Sequence (CRC-32) A.2.1.6. Generate and Insert Inter-Packet Gap
A.2.2. MAC RX Datapath x
A.2.2.1. Process RX Preamble A.2.2.2. Check RX Strict SFD A.2.2.3. Check RX FCS A.2.2.4. Handle RX Malformed Packet A.2.2.5. Remove PAD Bytes and FCS Bytes from RX Frames A.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors A.2.2.7. Inter-Packet Gap
A.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
A.2.3.1. Conditions Triggering XOFF Frame Transmission A.2.3.2. Conditions Triggering XON Frame Transmission A.2.3.3. Pause Control and Generation Interface A.2.3.4. Pause Control Frame Filtering
A.3. PCS, OTN, and FlexE Modes x
A.3.1. PCS Mode A.3.2. OTN Mode A.3.3. FlexE Mode
A.4. Precision Time Protocol Interface x
A.4.1. Features A.4.2. PTP User Flow A.4.3. Make PTP UI Adjustments A.4.4. Reference Time Interval A.4.5. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware)
A.4.2. PTP User Flow x
A.4.2.1. PTP TX User Flow A.4.2.2. PTP RX User Flow
A.4.3. Make PTP UI Adjustments x
A.4.3.1. Adjust TX UI A.4.3.2. Adjust RX UI
B. Appendix B: Configuration Registers x
B.1. Ethernet Avalon® Memory-Mapped Interface Address Space B.2. Packet Client Registers
1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide

4.1. Implement Required Clocking

This section describes the required clock connections and clock signals for various GTS Ethernet Intel® FPGA Hard IP core variations.

The following image shows the clock connection for Synchronous Adapter Modes.

Figure 12. Conceptual Overview of General IP Clock Connection for Synchronous Adapter Modes
The GTS Ethernet Intel® FPGA Hard IP requires two clock inputs:
  • i_clk_ref_p PMA reference clock
  • i_clk_sys datapath clock.

You can drive the PMA reference clock, i_clk_ref_p, from either local or regional clock pins. The local reference clock pin is bidirectional, except when there is a single GTS transceiver bank on an FPGA side, where it functions solely as an input reference clock pin. You can configure this bidirectional pin as an output for the Clock Data Recovery (CDR) recovered clock o_cdr_divclk from any of the four channels within the GTS transceiver bank. The device with a single GTS transceiver bank has a dedicated output pin for the CDR recovered clock. For more information about the GTS System PLL Intel® FPGA IP, refer to the GTS Transceiver PHY User Guide.

The output of the GTS System PLL Clocks Intel® FPGA IP drives the i_clk_sys datapath clock. The GTS System PLL Intel® FPGA IP sources its input reference clock i_refclk from either a local or regional reference clock pin.

The following figure shows all of the available clock inputs, clock outputs, and status signals when you generate the Ethernet Hard IP variant:
Figure 13. GTS Ethernet Intel® FPGA Hard IP Clock Signals and Clock Status

The following table describes the input and output clocks with required clock frequencies, and the clock-related status signals.

Table 17.  Clock Signals
Name Description
Clock Inputs
i_clk_tx

TX datapath clock

Drives the active TX Interface for the channel.

Clock source:

  • The o_clk_pll clock applies to MAC synchronous operation mode (If Enable asynchronous adapter clocks parameter is disabled).
  • In MAC asynchronous operation, drive this clock according to the frequency specified in Minimum Clock Rates for MAC Asynchronous Operation.
Clock frequencies:
  • 402.83203125MHz- Minimum EHIP system clock for 25GE No FEC/RS(528,514)/Firecode FEC channel.
  • 161.1328125 MHz- Minimum EHIP system clock for 10GE No FEC/Firecode FEC channel.
i_clk_rx

RX datapath clock

Drives the active RX Interface for the channel.

Clock source:
  • The o_clk_pll clock applies to MAC synchronous operation mode (If Enable asynchronous adapter clocks parameter is disabled).
  • In MAC asynchronous operation, drive this clock according to the frequency specified in Minimum Clock Rates for MAC Asynchronous Operation.
Clock frequencies:
  • 402.83203125MHz- Minimum EHIP system clock for 25GE No FEC/RS(528,514)/Firecode FEC channel.
  • 161.1328125 MHz- Minimum EHIP system clock for 10GE No FEC/Firecode FEC channel.
i_clk_sys

Ethernet system clock

Ethernet System Clock from GTS System PLL Clocks Intel® FPGA IP .
  • For 10GE, use 322.265625 MHz.
  • For 25GE, use 805.664062 MHz.
Note: The i_clk_sys is a virtual signal. In simulation, the signal appears as 0.
i_clk_ref_p
PMA Reference Clock
  • 156.25 MHz is the recommended frequency for all Ethernet modes.
  • 312.5 MHz is also supported when using without AN/LT.
  • 322.265625 MHz is supported when you select IEEE 802.3 BASE-R Firecode or RS(528,514), while using without AN/LT.
i_reconfig_clk

Avalon memory-mapped interface reconfiguration clock

Avalon® memory-mapped interface uses this clock to access control status registers (CSRs). This clock supports 100 to 125 MHz frequency.

i_clk_pll

PTP-related datapath clock

This clock drives the i_clk_tx and i_clk_rx when both, Enable IEEE 1588 PTP and Enable asynchronous adapter clocks parameters, are enabled.
Note: When Enable IEEE 1588 PTP parameter is disabled, tie this port to 1'b0.
i_pma_cu_clk

PMA Control Unit Clock

Connect this clock to o_pma_cu_clk output of the GTS Reset Sequencer Intel® FPGA IP . Refer to input and output signals of Connect the GTS Reset Sequencer Intel FPGA IP for more details.

i_pma_cu_clk

PMA Control Unit Clock

Connect this clock to o_pma_cu_clk output of the GTS Reset Sequencer Intel® FPGA IP . Refer to input and output signals of Connect the GTS Reset Sequencer Intel FPGA IP for more details.

Clock Outputs
o_clk_pll

System PLL clock

Clock derived from the GTS Ethernet Intel® FPGA Hard IP .

The frequency is the system PLL frequency divided by 2 (e.g., 806 MHz system PLL would result in a 403 MHz o_clk_pll)

  • 402.83203125 MHz Minimum EHIP system clock for 25GE No FEC/RS(528,514)/Firecode FEC Channel.
  • 161.1328125 MHz Minimum EHIP system clock for 10GE channels
o_clk_tx_div Clock derived from TX PLL. Its frequency is the data rate divided by 66.
  • For example, for 10GE (data rate is 10.3125 Gbps), the frequency is 10.3125 / 66 = 156.25 MHz (+/- 100 ppm).
  • For 25GE (data rate is 25,78125Gbps), the frequency is 25.78125 / 66 =390.625 MHz (+/- 100 ppm).
o_clk_rec_div64

This recovered clock is derived from the CDR. Its frequency is the data rate divided by 64.

  • 402.83203125 MHz (+/-100 ppm) for 25GE No FEC/RS (528,514) Firecode FEC channels.
  • 161.1328125 MHz(+/-100 ppm) for 10GE No FEC/Firecode FEC channels.
Note: The frequency is calculated as o_clk_tx_div.
o_clk_rec_div

This recovered clock is derived from the CDR. Its frequency is the data rate divided by 66.

  • 390.625 MHz (+/-100 ppm) for 25GE No FEC/ RS(528,514)/Firecode FEC channels.
  • 156.25 MHz (+/-100 ppm) for 10GE No FEC/Firecode FEC channels.
Note: The frequency is calculated as o_clk_tx_div.
o_cdr_divclk

Dedicated CDR divided clock output from PMA over the Local Reference Clock pins or dedicated CDR clock output pins. Refer to Figure 12

This clock is available when Enabled Dedicated CDR Clock Output is enabled in the IP parameter editor.

Table 18.  Clock Status
Name Description
i_syspll_lock Indicates that the Sys PLL IP is locked.
o_cdr_lock

This signal indicates that the recovered clocks are locked to data.

Do not use o_clk_rec_div64 or o_clk_rec_div until o_cdr_lock is high.

o_sys_pll_locked Indicates o_clk_pll is stable.
o_tx_pll_locked

TX SERDES PLLs are locked.

Do not use o_clk_tx_div until o_tx_pll_locked is high.


Section Content
Implement MAC Synchronous Clock Connections to Single Instance
Implement MAC Synchronous Clock Connections to Multiple Instances
Implement Clock Connections to MAC Asynchronous Operation
Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
Implement Clock Connections in PTP-Based Design

Related Information
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