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1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
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6.5.3. Run the Hardware Test
Follow these steps to test the hardware design example on the System Console:
- Open Tools > System Debugging Tools > System Console or type the command:
system-console &
- In the TCl Console window, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest.
- Type source main_10G.tcl to list the available JTAG masters.
- Type set_jtag <index> to select the appropriate JTAG master.
- Run one of the following commands:
- If you use the internal serial loopback, enter the following command:
run_test
- If you inserted an external loopback plug into the desired Ethernet port, enter the following command:
run_test_without_loopback
- If you use the internal serial loopback, enter the following command:
- Execute the run_test command to select the internal serial loopback. The script performs the following tasks:
- chkphy_status: Displays the clock frequencies and PMA PHY lock status.
- chkmac_status: Displays the MAC statistics counters.
- clear_all_stats: Clears the IP core statistics counters.
- start_pkt_gen: Starts the packet generator.
- stop_pkt_gen: Stops the packet generator.
- run_test: Turns on internal serial loopback.
- run_test_without_loopback: Turns off internal serial loopback.
- reg_read <addr>: Returns the IP core register value at <addr>. Example to read the TX datapath PCS ready register: Type reg_read 0x322.
- reg_write <addr> <data>: Writes <data> to the IP core register at address<addr>. Example to initiate soft reset on RX datapath: Type reg_write 0x108 0x0004.
- Verify that the output of the TCL script matches the output from a sample test run, shown below.
% run_test --- Turning off packet generation ---- -------------------------------------- --- Enabling Loopback... --- ---------------------------------------- Serial loopback on INST_NUM:0 Lane# 3 is disabled ---Asserting CSR RX Reset ---- Value from issp reset probe is 0xcd/0b11001101 1. 0x6A340 2. 0x0006a340 Polling Successfull Bit 15: 0x000001 , Bit 14: 0x000000 1. 0x62340 2. 0x00062340 Polling Successfull Bit 15: 0x000000 , Bit 14: 0x000000 ---Releasing CSR Reset ---- Serial loopback on INST_NUM:0 Lane# 3 is enabled .............Wait for RX clock to settle... -------- Printing PHY status --------- -------------------------------------- RX PHY Register Access: Checking Clock Frequencies(KHz) TXCLK :161130 (KHZ) RXCLK :161130 (KHZ) TX PLL Lock Status 0x00000001 RX Frequency Lock Status 0x00000001 RX PCS Ready 0x1 TX Lanes Stable 0x1 Deskewed status 0x0 Link Fault Status 0x00000000 RX Frame Error 0x00000000 RX AM LOCK Condition 0x1 ---- Clearing packet counters -------------------------- --- IP_INST[0]----- -------------------------------------------------------- --- --------- Sending packets... --------- -------------------------------------- ----- Reading packet counters ----- -------------------------------------- Tx Start Packet Counter :16 Tx End Packet Counter :16 Rx Start Packet Counter :16 Rx End Packet Counter :16 Rx Error Counter :0 -------------------------------------- run_test:pass -------------------------------------- ---------------- Done ---------------- Serial loopback on INST_NUM:0 Lane# 3 is enabled ---Asserting CSR RX Reset ---- Value from issp reset probe is 0xcd/0b11001101 1. 0x0A340 2. 0x0000a340 Polling Successfull Bit 15: 0x000001 , Bit 14: 0x000000 1. 0x02340 2. 0x00002340 Polling Successfull Bit 15: 0x000000 , Bit 14: 0x000000 ---Releasing CSR Reset ---- Serial loopback on INST_NUM:0 Lane# 3 is disabled