GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

6.5.3. Run the Hardware Test

Follow these steps to test the hardware design example on the System Console:
  1. Open Tools > System Debugging Tools > System Console or type the command:
    system-console &
  2. In the TCl Console window, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest.
  3. Type source main_10G.tcl to list the available JTAG masters.
  4. Type set_jtag <index> to select the appropriate JTAG master.
  5. Run one of the following commands:
    • If you use the internal serial loopback, enter the following command:
      run_test
    • If you inserted an external loopback plug into the desired Ethernet port, enter the following command:
      run_test_without_loopback
  6. Execute the run_test command to select the internal serial loopback. The script performs the following tasks:
    • chkphy_status: Displays the clock frequencies and PMA PHY lock status.
    • chkmac_status: Displays the MAC statistics counters.
    • clear_all_stats: Clears the IP core statistics counters.
    • start_pkt_gen: Starts the packet generator.
    • stop_pkt_gen: Stops the packet generator.
    • run_test: Turns on internal serial loopback.
    • run_test_without_loopback: Turns off internal serial loopback.
    • reg_read <addr>: Returns the IP core register value at <addr>. Example to read the TX datapath PCS ready register: Type reg_read 0x322.
    • reg_write <addr> <data>: Writes <data> to the IP core register at address<addr>. Example to initiate soft reset on RX datapath: Type reg_write 0x108 0x0004.
  7. Verify that the output of the TCL script matches the output from a sample test run, shown below.
    % run_test
    --- Turning off packet generation ----
    --------------------------------------
    --- Enabling Loopback... ---
    ----------------------------------------
    Serial loopback on INST_NUM:0 Lane# 3 is disabled
    
    ---Asserting CSR RX Reset ----
    Value from issp reset probe is 0xcd/0b11001101
    1. 0x6A340 	 
    2. 0x0006a340	 
    Polling Successfull Bit 15: 0x000001 , Bit 14: 0x000000
    1. 0x62340	 
    2. 0x00062340	 
    Polling Successfull Bit 15: 0x000000 , Bit 14: 0x000000
    ---Releasing CSR Reset ---- 
     	 	 
    Serial loopback on INST_NUM:0 Lane# 3 is enabled
    .............Wait for RX clock to settle... 
    
    -------- Printing PHY status ---------
    --------------------------------------
     RX PHY Register Access: Checking Clock Frequencies(KHz)
    	TXCLK 		:161130  (KHZ) 
    	RXCLK 		:161130  (KHZ) 
    
     TX PLL Lock Status           0x00000001 
     RX Frequency Lock Status     0x00000001 
     RX PCS Ready                 0x1
     TX Lanes Stable              0x1
     Deskewed status                0x0
     Link Fault Status            0x00000000
     RX Frame Error               0x00000000
     RX AM LOCK Condition         0x1 
    
    ---- Clearing packet counters --------------------------
    ---  IP_INST[0]-----
    --------------------------------------------------------
    ---
    
    --------- Sending packets... ---------
    --------------------------------------
     
    ----- Reading packet counters -----
    --------------------------------------
     
    Tx Start Packet Counter :16
    Tx End Packet Counter   :16
    Rx Start Packet Counter :16
    Rx End Packet Counter   :16
    Rx Error Counter        :0
    --------------------------------------
    
    run_test:pass
    --------------------------------------
    
    ---------------- Done ----------------
     
     Serial loopback on INST_NUM:0 Lane# 3 is enabled 
     
    ---Asserting CSR RX Reset ---- 
    Value from issp reset probe is 0xcd/0b11001101
     1. 0x0A340 
     2. 0x0000a340
    Polling Successfull Bit 15: 0x000001 , Bit 14: 0x000000
     1. 0x02340
     2. 0x00002340
    Polling Successfull Bit 15: 0x000000 , Bit 14: 0x000000
    ---Releasing CSR Reset ---- 
     
     Serial loopback on INST_NUM:0 Lane# 3 is disabled