Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

2.2.12.1. Power-Up Calibration

After device power-up, the I/O manager automatically initiates the calibration process. The process continues during device programming.

You must enable the permit_cal signal from the IOPLL IP core to delay the power-up calibration in I/O PLL if the reference clock is not stable before device configuration. Set permit_cal = 0 upon power up until the reference clock is stable and operating at the correct frequency. Then, set permit_cal = 1 to initiate the power-up calibration. You must ensure that the permit_cal signal remains high once asserted.

Figure 22. Example of Power-Up Calibration When PLL Reference Clock is Not Stable Upon Power UpThis is an example on how to set permit_cal = 0 when the PLL reference clock is not stable before device configuration. You can invert the I/O PLL reset signal and connect it to the permit_cal port as shown in this figure. Asserting the reset signal high delays power-up calibration. Deassert the reset signal once the clock driving the I/O PLL is stable to initiate the power-up calibration.