Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

2.1.2. Clock Resources

Table 1.   Stratix® 10 Clock Input Pins Resources
Device Number of Resources Available Source of Clock Resource
  • TX 400

Transceiver: 9 differential

I/O: 32 single-ended or 16 differential

For Transceiver pins: REFCLK_GXB[L,R][1,4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T][p,n]

For I/O pins: CLK_[2,3][A..N]_[0,1][p,n]

  • GX 400
  • SX 400

Transceiver: 24 differential

I/O: 32 single-ended or 16 differential

  • GX 650
  • SX 650

Transceiver: 48 differential

I/O: 32 single-ended or 16 differential

  • GX 850
  • GX 1100
  • SX 850
  • SX 1100

Transceiver: 32 differential

I/O: 60 single-ended or 30 differential

  • TX 850
  • TX 1100

Transceiver: 26 differential

I/O: 36 single-ended or 18 differential

  • DX 1100

Transceiver: 11 differential

I/O: 22 single-ended or 44 differential

  • GX 1650
  • GX 2100
  • SX 1650
  • SX 2100

Transceiver: 32 differential

I/O: 56 single-ended or 28 differential

  • MX 1650
  • MX 2100

Transceiver: 32 differential

I/O: 52 single-ended or 26 differential

  • TX 1650
  • TX 2100

Transceiver: 35 differential

I/O: 36 single-ended or 18 differential

  • DX 2100

Transceiver: 15 differential

I/O: 48 single-ended or 14 differential

  • GX 1660
  • GX 2110

Transceiver: 16 differential

I/O: 56 single-ended or 28 differential

  • GX 2500
  • GX 2800
  • SX 2500
  • SX 2800

Transceiver: 32 differential

I/O: 96 single-ended or 48 differential

  • TX 2500
  • TX 2800

Transceiver: 53 differential

I/O: 36 single-ended or 18 differential

  • DX 2800

Transceiver: 13 differential

I/O: 68 single-ended or 34 differential

Table 2.   Stratix® 10 Programmable Clock Routing Resources
Device Number of Resources Available Source of Clock Resource
All Stratix® 10 devices 32 bidirectional programmable clock routing at the boundary of each clock sector

For transceiver bank:

  • Physical medium attachment (PMA) and physical coding sublayer (PCS) TX and RX clocks per channel
  • PMA and PCS TX and RX divide clocks per channel
  • Hard IP core clock output signals
  • Fractional PLL (fPLL) C counter outputs
  • REFCLK pins
  • Core signals 1

For I/O bank:

  • I/O PLL C counter outputs
  • I/O PLL M counter outputs for feedback
  • Clock input pins
  • Core signals 1
  • Dynamic phase alignment (DPA) clock output
  • Phase aligner counter outputs

For more information about the clock input pins connections, refer to the pin connection guidelines.

1 Core signals drive directly to programmable clock routing through clock switch multiplexers in the clock sector instead of the periphery DCM block.