Visible to Intel only — GUID: mcn1440577973464
Ixiasoft
Visible to Intel only — GUID: mcn1440577973464
Ixiasoft
2.1.2. Clock Resources
Device | Number of Resources Available | Source of Clock Resource |
---|---|---|
|
Transceiver: 9 differential I/O: 32 single-ended or 16 differential |
For Transceiver pins: REFCLK_GXB[L,R][1,4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T][p,n] For I/O pins: CLK_[2,3][A..N]_[0,1][p,n] |
|
Transceiver: 24 differential I/O: 32 single-ended or 16 differential |
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Transceiver: 48 differential I/O: 32 single-ended or 16 differential |
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Transceiver: 32 differential I/O: 60 single-ended or 30 differential |
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Transceiver: 26 differential I/O: 36 single-ended or 18 differential |
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Transceiver: 11 differential I/O: 22 single-ended or 44 differential |
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Transceiver: 32 differential I/O: 56 single-ended or 28 differential |
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Transceiver: 32 differential I/O: 52 single-ended or 26 differential |
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Transceiver: 35 differential I/O: 36 single-ended or 18 differential |
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Transceiver: 15 differential I/O: 48 single-ended or 14 differential |
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Transceiver: 16 differential I/O: 56 single-ended or 28 differential |
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Transceiver: 32 differential I/O: 96 single-ended or 48 differential |
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Transceiver: 53 differential I/O: 36 single-ended or 18 differential |
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Transceiver: 13 differential I/O: 68 single-ended or 34 differential |
Device | Number of Resources Available | Source of Clock Resource |
---|---|---|
All Stratix® 10 devices | 32 bidirectional programmable clock routing at the boundary of each clock sector | For transceiver bank:
For I/O bank:
|
For more information about the clock input pins connections, refer to the pin connection guidelines.