Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide

Document Version Quartus® Prime Version Changes
2024.07.11 24.1 Updated the description for Automatic Switchover with Manual Overide mode from high to low in the Table: IOPLL IP Core Parameters - Settings Tab for Stratix® 10 Devices.
2024.04.01 24.1 Removed a note to the Ensure glitch free clock switchover parameter description in the Clock Control IP Core Parameters for Stratix® 10 Devices table.
2023.09.08 20.3 Updated Figure: I/O PLL High-Level Block Diagram for Stratix® 10 Devices.
2022.08.16 20.3
  • Added a note in the Clock Sector section.
2021.09.21 20.3
  • Added a note in the PLL Architecture section.
  • Added description on PLL loses lock in the Locked section.
  • Updated the Manual Switchover mode description for the Switchover Mode parameter in the IOPLL IP Core Parameters - Settings Tab for Stratix® 10 Devices table.
2021.06.21 20.3
  • Removed the Preliminary tag for the PLL Features in Stratix® 10 Devices table.
  • Added footnote to the My reference clock frequency might change parameter description in the IOPLL IP Core Parameters - PLL Tab for Stratix® 10 Devices table.
2020.09.28 20.3 Added the IP-XACT File Generation section under IOPLL Intel® FPGA IP Core.
2020.03.06 19.3 Added description about the bidirectional I/O pin must not be globally promoted in the Zero-Delay Buffer Mode section.
2019.12.10 19.3 Added a guideline for design with encrypted IOPLL Intel® FPGA IP core in the IP Core Constraints section.
2019.10.17 19.3
  • Updated the Stratix® 10 Clock Input Pins Resources table.
    • Added Stratix® 10 TX 400, DX 1100, DX 2100, and DX 2800.
    • Updated the number of resources available for Stratix® 10 GX 1650, GX 2100, SX 1650, and SX 2100.
  • Updated N counter divide factor range for fractional PLL from '1 to 32' to '1 to 31' in the PLL Features in Stratix® 10 Devices table.
  • Updated Clock Control Intel FPGA IP core to version 19.1.0.
    • Updated IP name from Clock Control Intel Stratix 10 FPGA IP core to Clock Control Intel FPGA IP core.
  • Added release information for each IP core.
2019.07.01 19.2
  • Updated the Stratix® 10 Clock Input Pins Resources table.
    • Added Stratix® 10 devices: TX 850, TX 1100, GX 1660, and GX 2110.
    • Removed unsupported Stratix® 10 devices: MX 1100, GX 4500, GX 5500, SX 4500, and SX 5500.
    • Updated the number of resources available for Stratix® 10 TX 1650 and TX 2100.
  • Updated the description in the Root Clock Gate section.
  • Added new guideline topics:
    • Guideline: I/O PLL Jitter Performance
    • Guideline: Clock Gating
2018.12.24 18.1
  • Updated the I/O PLL High-Level Block Diagram for Stratix® 10 Devices.
  • Updated the Power-Up Calibration section.
  • Added the constraints for IOPLL IP core in the IP Core Constraints section.
  • Added information on advanced mode reconfiguration in the following sections:
    • Guideline: I/O PLL Reconfiguration
    • IOPLL Reconfig Intel Stratix 10 FPGA IP Core
    • IOPLL Reconfig IP Core Reconfiguration Modes
  • Updated the steps to perform I/O PLL reconfiguration using advanced mode in the Advanced Mode Reconfiguration section.
  • Added Design Example 2: Advanced Mode Reconfiguration Using IOPLL Reconfig IP Core.
2018.08.03 18.0 Added diagrams on PLL cascading connectivity in the PLL Cascading section.
2018.05.07 18.0
  • Added a link to the Design Recommendations User Guide for details on clock assignments in the Quartus® Prime software.
  • Clarified that the dynamic clock switchover can be optionally made glitch free using additional external soft logic.
  • Added note about the non-dedicated feedback path for the source synchronous compensation mode and normal compensation mode in the PLL Features in Stratix® 10 Devices table.
  • Added note about the non-dedicated feedback path for the source synchronous compensation mode and normal compensation mode in the I/O PLL High-Level Block Diagram for Stratix® 10 Devices diagram.
  • Updated the core clock compensation methods in the Clock Feedback Modes section.
  • Updated the Direct Compensation Mode section.
  • Added information on non-dedicated feedback path in normal or source synchronous compensation mode in the Clock Multiplication and Division section.
  • Updated the PLL Cascading section.
  • Updated the description in the following sections to mention that the mgmt_clk and scanclk signals must be free running.
    • Guideline: I/O PLL Reconfiguration
    • Avalon® -MM Interface Ports in the IOPLL Reconfig IP Core for Stratix® 10 Devices
  • Added information on advanced mode configuration.
    • Added the advanced mode configuration in the IOPLL Reconfig IP Core Reconfiguration Modes table.
    • Added new section: Advanced Mode Reconfiguration.
    • Added new table: Address Bus and Data Bus Settings for Advanced Mode Reconfiguration.
    • Added new table: Data Bus Setting for Bandwidth Control and Charge Pump.
    • Added new table: Data Bus Setting for Ripplecap.
  • Added a note on recalibration for .mif streaming reconfiguration in the .mif Streaming Reconfiguration section.
  • Corrected step 3 in the Dynamic Phase Shift Reconfiguration section.
  • Corrected the waveforms for mgmt_address[7:0] and mgmt_writedata[7:0] in the Waveform Example for .mif Streaming Reconfiguration Design Example diagram.
  • Removed the dynamic phase shift feature for fPLL in the following sections:
    • Removed phase shift resolution for fPLL and updated the note to phase shift resolution in the PLL Features in Stratix® 10 Devices table.
    • Removed description on fPLL in the Programmable Phase Shift section.
    • Removed description on fPLL in the PLL Reconfiguration and Dynamic Phase Shift section.
  • Added Compensated Outclk and Use Nondedicated Feedback Path parameters in the IOPLL IP Core Parameters - PLL Tab for Stratix® 10 Devices table.
  • Added Create a permit_cal signal to connect with an upstream PLL parameter in the IOPLL IP Core Parameters - Cascading Tab table.
  • Added permit_cal port in the IOPLL Ports for Stratix® 10 Devices table.
  • Renamed the following IP cores as per Intel rebranding:
    • Renamed Intel FPGA IOPLL Reconfig IP core to IOPLL Reconfig Intel FPGA IP core.
    • Renamed Intel FPGA IOPLL IP core to IOPLL Intel FPGA IP core.
    • Renamed Stratix 10 Clock Control IP core to Clock Control Intel Stratix 10 FPGA IP core.
Date Version Changes
December 2017 2017.12.07
  • Updated the Dedicated Clock Resources Within a Clock Sector diagram.
  • Updated description in the Programmable Clock Routing section.
  • Updated Stratix® 10 Clock Input Pins Resources table.
    • Added resources for Stratix® 10 TX and MX devices.
    • Updated resources for the following devices:
      • GX 1650
      • GX 2100
      • SX 1650
      • SX 2100
      • GX 2500
      • GX 2800
      • SX 2500
      • SX 2800
  • Added note to core signals in Stratix® 10 Programmable Clock Routing Resources table.
  • Updated Clock Gating and Clock Divider in Stratix® 10 Clock Network diagram.
  • Added links and updated description in the Root Clock Gate section.
  • Added links and updated description in the Sector Clock Gate section.
  • Updated the Clock Gating Timing Diagram.
  • Updated description in the Clock Divider section.
  • Updated PLL Features in Stratix® 10 Devices table.
    • Updated C counter divide factors for I/O PLL.
    • Updated the note to phase shift resolution and updated the phase shift resolution for fPLL.
  • Updated the Reset section.
    • Updated the note about the conditions to reset the I/O PLL.
    • Removed description on fPLL reset signal (pll_powerdown).
  • Updated the description in the following sections.
    • Clock Feedback Modes
    • Direct Compensation Mode
    • Source Synchronous Compensation Mode
    • Normal Compensation Mode
  • Updated the description in the PLL Cascading section.
  • Added a requirement for automatic clock switchover mode.
  • Updated description in the Manual Clock Switchover section.
  • Removed the guidelines on PLL reconfiguration using .mif streaming in the Guideline: Configuration Constraints section.
  • Added design examples for IOPLL and IOPLL Reconfig IP cores.
  • Updated port names in the Connectivity between the IOPLL and IOPLL Reconfig IP Cores in the Quartus® Prime Software diagram.
  • Updated reconfig_from_pll[9..0] to reconfig_from_pll[10..0] in the following sections:
    • Connectivity between the IOPLL and IOPLL Reconfig IP Cores in the Quartus® Prime Software diagram
    • Connecting the IOPLL and IOPLL Reconfig IP Cores section
    • Avalon® -MM Interface Ports in the IOPLL Reconfig IP Core section
  • Added a note to the IOPLL Reconfig IP Core Reconfiguration Modes table.
  • Updated the Clock Control IP Core Parameters for Stratix® 10 Devices table.
    • Updated Ensure glitch free clock switchover description.
    • Updated Clock Enable Type description.
    • Updated Enable Register Mode value and description.
  • Updated Multiply Factor (M-Counter) legal value in the IOPLL IP Core Parameters - PLL Tab for Stratix® 10 Devices table.
  • Updated IOPLL IP Core Parameters - Settings Tab for Stratix® 10 Devices table.
    • Updated parameter from Enable access to PLL LVDS_CLK/LOADEN output port to Access to PLL LVDS_CLK/LOADEN output port, the legal value, and description.
  • Updated extswitch description in the IOPLL Ports for Stratix® 10 Devices table.
  • Updated updn description in the Dynamic Phase Shift Ports in the IOPLL IP Core table.
  • Updated descriptions for data[3] and data[7:4] in the Data Bus Setting for Dynamic Phase Shift for IOPLL Reconfig IP Core table.
  • Updated the following terms:
    • Changed LogicLock Plus to Logic Lock
    • Changed TimeQuest Timing Analyzer to Timing Analyzer
  • Updated the following IP names:
    • Changed Altera IOPLL to IOPLL
    • Changed Altera IOPLL Reconfig to IOPLL Reconfig
    • Changed Altera In-System Sources & Probe to In-System Sources & Probes
May 2017 2017.05.26
  • Updated the following sections:
    • Clock Sector
    • Programmable Clock Routing
    • Internal Logic
    • Zero-Delay Buffer Mode
    • External Feedback Mode
    • User Calibration
  • Updated the default feedback mode for normal and source synchronous compensation modes.
  • Updated scale factor for Post-Scale Counter, L in Clock Multiplication and Division section.
  • Updated minimum phase shift increment for fPLL in the following sections:
    • Programmable Phase Shift
    • PLL Reconfiguration and Dynamic Phase Shift
  • Changed CLKUSR to OSC_CLK_1 in PLL Calibration section.
  • Updated IOPLL IP core.
  • Added Stratix® 10 Clocking and PLL Design Considerations chapter.
  • Added IOPLL Reconfig IP core.
October 2016 2016.10.31 Initial release.