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1. Stratix® 10 Clocking and PLL Overview
2. Stratix® 10 Clocking and PLL Architecture and Features
3. Stratix® 10 Clocking and PLL Design Considerations
4. Stratix® 10 Clocking and PLL Implementation Guides
5. Clock Control Intel® FPGA IP Core References
6. IOPLL Intel® FPGA IP Core References
7. IOPLL Reconfig Intel® FPGA IP Core References
8. Stratix® 10 Clocking and PLL User Guide Archives
9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Architecture
2.2.4. PLL Control Signals
2.2.5. Clock Feedback Modes
2.2.6. Clock Multiplication and Division
2.2.7. Programmable Phase Shift
2.2.8. Programmable Duty Cycle
2.2.9. PLL Cascading
2.2.10. Clock Switchover
2.2.11. PLL Reconfiguration and Dynamic Phase Shift
2.2.12. PLL Calibration
4.3.4.1. Design Example 1: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.2. Design Example 2: Advanced Mode Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.3. Design Example 3: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.4. Design Example 4: Dynamic Phase Shift Using IOPLL Reconfig IP Core
Visible to Intel only — GUID: mcn1440763386836
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9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide
Document Version | Quartus® Prime Version | Changes |
---|---|---|
2024.07.11 | 24.1 | Updated the description for Automatic Switchover with Manual Overide mode from high to low in the Table: IOPLL IP Core Parameters - Settings Tab for Stratix® 10 Devices. |
2024.04.01 | 24.1 | Removed a note to the Ensure glitch free clock switchover parameter description in the Clock Control IP Core Parameters for Stratix® 10 Devices table. |
2023.09.08 | 20.3 | Updated Figure: I/O PLL High-Level Block Diagram for Stratix® 10 Devices. |
2022.08.16 | 20.3 |
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2021.09.21 | 20.3 |
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2021.06.21 | 20.3 |
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2020.09.28 | 20.3 | Added the IP-XACT File Generation section under IOPLL Intel® FPGA IP Core. |
2020.03.06 | 19.3 | Added description about the bidirectional I/O pin must not be globally promoted in the Zero-Delay Buffer Mode section. |
2019.12.10 | 19.3 | Added a guideline for design with encrypted IOPLL Intel® FPGA IP core in the IP Core Constraints section. |
2019.10.17 | 19.3 |
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2019.07.01 | 19.2 |
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2018.12.24 | 18.1 |
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2018.08.03 | 18.0 | Added diagrams on PLL cascading connectivity in the PLL Cascading section. |
2018.05.07 | 18.0 |
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Date | Version | Changes |
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December 2017 | 2017.12.07 |
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May 2017 | 2017.05.26 |
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October 2016 | 2016.10.31 | Initial release. |