Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

3.5. Guideline: Timing Closure

For timing closure, refer to the following guidelines:

  • Reconfiguring a PLL's counter and loop filter settings changes both the output frequency and the clock uncertainty of that I/O PLL. Dynamic phase shift only affects the output clock phase.
  • The Timing Analyzer in the Quartus® Prime software performs timing analysis for the initial PLL settings only. You must verify that your design closes timing after dynamic reconfiguration or dynamic phase shift.
  • Intel recommends compiling the I/O PLL designs with each intended configuration setting to determine the variation in the clock with the I/O PLL settings.