Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

3.2. IP Core Constraints

To implement the fPLL IP core, you must adhere to the following constraints:

  • You must use create_clock constraints on fPLL reference clocks on the project's top-level Synopsys Design Constraints File (.sdc).
  • Any SDC design constraints referring to transceiver clocks must be listed after the transceiver Native PHY .sdc file constraints.
  • fPLL output clocks have no phase relationship to the reference clock when utilizing the fPLL output clocks for core usage. The fPLL output clocks of the clock divider are still in phase with each other, however.

To implement the IOPLL IP core, you must adhere to the following constraints:

  • Any SDC design constraints referring to the I/O PLL clocks must be listed after the SDC constraints for the IOPLL IP core.
  • For Quartus® Prime software version 18.1 or later, you may see error warning message for design with encrypted IOPLL IP core. The auto-generated .sdc files of the IOPLL IP core are not supported if you use encryption. You must manually create the .sdc file using create_clock and create_generated_clock to replace the auto-generated .sdc file in the design for refclk and output clocks.