Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

3.8. Guideline: Clock Gating

Both sector clock gate and root clock gate have similar skews. To achieve higher performance when transferring between gated and non-gated clocks and vice-versa, refer to the following guidelines:

  • Minimize the size of clock region because smaller clock delays have lower skew.
  • Ensure that both gated and non-gated clocks have similar sizes.
  • Minimize logic on paths between gated and non-gated clocks to achieve better timing margin to compensate for the higher skews.