Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

3.7. Guideline: I/O PLL Jitter Performance

To achieve the Stratix® 10 I/O PLL clock output jitter performance as specified in the Stratix® 10 Device Datasheet, adhere to the maximum allowable number of unterminated simultaneously switching output (SSO) pins, such as LVTTL and LVCMOS, within the I/O bank (where the PLL output clock resides).

Table 4.  Maximum Allowable Number of Unterminated SSO Pins Within an I/O Bank
SSO Pin Current Strength (mA) Maximum Allowable Number of SSO Pins
16 17
12 21
10 27
8 36

If you use more than the maximum allowable unterminated SSO pins, additional jitter beyond the PLL clock output jitter specification is induced to the PLL clock output.

Table 5.  Jitter Increment per SSO Pin When the Unterminated SSO Pin Utilization of the Affected I/O Bank Exceeds the Maximum Allowable Number
SSO Pin Current Strength (mA) Jitter Increment per SSO Pin (ps/pin)
16 8
12 7
10 6
8 4

When you use a combination of different current strength, calculate the maximum allowable number of SSO pins according to the strongest current strength used. The jitter increment value per SSO pin should then be calculated using the strongest current strength setting from the remaining SSO pins (after deducting the maximum allowable number of SSO pins from the total SSO pins). For example, if the design has 19 pins with current strength 16 mA, 5 pins with current strength 12 mA, and 2 pins with current strength 10 mA, the maximum allowable number of SSO pins for this design is 17, and the jitter increment per SSO pin is 8 ps/pin. Total additional jitter induced is equivalent to [(19 + 5 + 2) – 17] × 8 = 72 ps.