Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

2.1.1. Clock Network Architecture

Each Stratix® 10 device is divided into a number of evenly sized clock sectors.

Figure 1. Clock Sector Floorplan for Stratix® 10 DevicesThis figure shows an example of the clock sectors in an Stratix® 10 device, which is implemented as an array of sectors—12 rows and 9 columns in this example. Clock sectors are vertically aligned to match the height of transceiver and I/O banks. I/O banks are contained within the clock sectors. Transceiver bank interfaces are always located beside the clock sectors, at the left or right side of the device.