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1. Stratix® 10 Clocking and PLL Overview
2. Stratix® 10 Clocking and PLL Architecture and Features
3. Stratix® 10 Clocking and PLL Design Considerations
4. Stratix® 10 Clocking and PLL Implementation Guides
5. Clock Control Intel® FPGA IP Core References
6. IOPLL Intel® FPGA IP Core References
7. IOPLL Reconfig Intel® FPGA IP Core References
8. Stratix® 10 Clocking and PLL User Guide Archives
9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Architecture
2.2.4. PLL Control Signals
2.2.5. Clock Feedback Modes
2.2.6. Clock Multiplication and Division
2.2.7. Programmable Phase Shift
2.2.8. Programmable Duty Cycle
2.2.9. PLL Cascading
2.2.10. Clock Switchover
2.2.11. PLL Reconfiguration and Dynamic Phase Shift
2.2.12. PLL Calibration
4.3.4.1. Design Example 1: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.2. Design Example 2: Advanced Mode Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.3. Design Example 3: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.4. Design Example 4: Dynamic Phase Shift Using IOPLL Reconfig IP Core
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4.3.3.4. Dynamic Phase Shift Reconfiguration
The dynamic phase shifts reconfiguration can determine the number of shifts, the direction of the phase shift and the output clock to be shifted.
To perform dynamic phase shift reconfiguration through the IOPLL Reconfig IP core, follow these steps:
- Set mgmt_address[9:8] to 2’b11 to select dynamic phase shift reconfiguration mode.
- set mgmt_writedata[7:0] to indicate the desired number of phase shift, the direction of phase shift, and the desired counter to be shifted.
- To start the dynamic phase shift reconfiguration on the I/O PLL, assert the mgmt_write signal for one mgmt_clk cycle. This signal is the equivalent of the phase_en signal on the I/O PLL.
- After the dynamic phase shift is complete, the mgmt_waitrequest signal is de-asserted.
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