Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

2.1.3.1. Dedicated Clock Input Pins

The sources of dedicated clock input pins are as follows:

  • fPLL—REFCLK_GXB[L,R][1,4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T][p,n] from transceiver column
  • I/O PLL—CLK_[2,3][A..N]_[0,1][p,n] from I/O column

You can use the dedicated clock input pins for high fan-out control signals, such as asynchronous clears, presets, and clock enables, for protocol signals through the programmable clock routing.

The dedicated clock input pins for an I/O PLL can be either differential clocks or single-ended clocks. The dedicated clock input pins for fPLL only support differential clocks and do not support single-ended clocks.

Driving a PLL over programmable clock routing can cause higher jitter at the PLL input, and the PLL is not able to fully compensate for the programmable clock routing. Intel recommends using the dedicated clock input pins for optimal performance to drive the PLLs.