Visible to Intel only — GUID: mcn1440655748127
Ixiasoft
1. Stratix® 10 Clocking and PLL Overview
2. Stratix® 10 Clocking and PLL Architecture and Features
3. Stratix® 10 Clocking and PLL Design Considerations
4. Stratix® 10 Clocking and PLL Implementation Guides
5. Clock Control Intel® FPGA IP Core References
6. IOPLL Intel® FPGA IP Core References
7. IOPLL Reconfig Intel® FPGA IP Core References
8. Stratix® 10 Clocking and PLL User Guide Archives
9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Architecture
2.2.4. PLL Control Signals
2.2.5. Clock Feedback Modes
2.2.6. Clock Multiplication and Division
2.2.7. Programmable Phase Shift
2.2.8. Programmable Duty Cycle
2.2.9. PLL Cascading
2.2.10. Clock Switchover
2.2.11. PLL Reconfiguration and Dynamic Phase Shift
2.2.12. PLL Calibration
4.3.4.1. Design Example 1: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.2. Design Example 2: Advanced Mode Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.3. Design Example 3: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.4. Design Example 4: Dynamic Phase Shift Using IOPLL Reconfig IP Core
Visible to Intel only — GUID: mcn1440655748127
Ixiasoft
2.2.1. PLL Features
Feature | Fractional PLL | I/O PLL |
---|---|---|
Integer PLL | Yes | Yes |
Fractional PLL | Yes | — |
Number of C output counter | 1 | 9 |
M counter divide factor range | In integer mode: 8 to 127 In fractional mode: 11 to 123 |
4 to 160 |
N counter divide factor range | 1 to 31 | 1 to 110 |
C counter divide factor range | 1 to 512 | 1 to 510 |
L counter divide factors | 1, 2, 4, and 8 | — |
Dedicated external clock outputs | — | Yes |
Dedicated clock input pins | Yes | Yes |
External feedback input pin | — | Yes |
Spread-spectrum input clock tracking 2 | Yes | Yes |
Source synchronous compensation 3 | — | Yes |
Direct compensation | Yes | Yes |
Normal compensation 3 | — | Yes |
Zero-delay buffer compensation | — | Yes |
External feedback compensation | — | Yes |
LVDS compensation | — | Yes |
Voltage-controlled oscillator (VCO) output drives the DPA clock | — | Yes |
Phase shift resolution 4 | — | 78.125 ps |
Programmable duty cycle | Fixed 50% duty cycle | Yes |
Power down mode | Yes | Yes |
2 Provided input clock jitter is within input jitter tolerance specifications.
3 Non-dedicated feedback path option is available for this compensation mode.
4 The smallest phase shift is determined by the VCO period divided by eight (for I/O PLL). For degree increments, the Stratix® 10 device can shift all output frequencies in increments of at least 45° (for I/O PLL). Smaller degree increments are possible depending on the frequency and divide parameters.