Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

2.2.1. PLL Features

Table 3.  PLL Features in Stratix® 10 Devices
Feature Fractional PLL I/O PLL
Integer PLL Yes Yes
Fractional PLL Yes
Number of C output counter 1 9
M counter divide factor range

In integer mode: 
8 to 127

In fractional mode: 
11 to 123

4 to 160
N counter divide factor range 1 to 31 1 to 110
C counter divide factor range 1 to 512 1 to 510
L counter divide factors 1, 2, 4, and 8
Dedicated external clock outputs Yes
Dedicated clock input pins Yes Yes
External feedback input pin Yes
Spread-spectrum input clock tracking 2 Yes Yes
Source synchronous compensation 3 Yes
Direct compensation Yes Yes
Normal compensation 3 Yes
Zero-delay buffer compensation Yes
External feedback compensation Yes
LVDS compensation Yes
Voltage-controlled oscillator (VCO) output drives the DPA clock Yes
Phase shift resolution 4 78.125 ps
Programmable duty cycle Fixed 50% duty cycle Yes
Power down mode Yes Yes
2 Provided input clock jitter is within input jitter tolerance specifications.
3 Non-dedicated feedback path option is available for this compensation mode.
4 The smallest phase shift is determined by the VCO period divided by eight (for I/O PLL). For degree increments, the Stratix® 10 device can shift all output frequencies in increments of at least 45° (for I/O PLL). Smaller degree increments are possible depending on the frequency and divide parameters.