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1. Stratix® 10 Clocking and PLL Overview
2. Stratix® 10 Clocking and PLL Architecture and Features
3. Stratix® 10 Clocking and PLL Design Considerations
4. Stratix® 10 Clocking and PLL Implementation Guides
5. Clock Control Intel® FPGA IP Core References
6. IOPLL Intel® FPGA IP Core References
7. IOPLL Reconfig Intel® FPGA IP Core References
8. Stratix® 10 Clocking and PLL User Guide Archives
9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Architecture
2.2.4. PLL Control Signals
2.2.5. Clock Feedback Modes
2.2.6. Clock Multiplication and Division
2.2.7. Programmable Phase Shift
2.2.8. Programmable Duty Cycle
2.2.9. PLL Cascading
2.2.10. Clock Switchover
2.2.11. PLL Reconfiguration and Dynamic Phase Shift
2.2.12. PLL Calibration
4.3.4.1. Design Example 1: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.2. Design Example 2: Advanced Mode Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.3. Design Example 3: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.4. Design Example 4: Dynamic Phase Shift Using IOPLL Reconfig IP Core
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4.2.5.1. Design Example: Dynamic Phase Shift Using IOPLL IP Core
This design example uses the same design as "Design Example 3: Dynamic Phase Shift Using IOPLL Reconfig IP Core" without using the IOPLL Reconfig Intel® FPGA IP core. This design example demonstrates the implementation of the I/O PLL dynamic phase shift directly through the IOPLL IP core.
To run the test with this design example, perform these steps:
- Download and restore the iopll-dynamic-phase-shift.qar file.
- Change the device and pin assignments of the design example to match your hardware.
- Recompile the design example. Ensure that the design example does not contain any timing violation after recompilation.
- Open the AN.stp file and program the device with top.sof.
- Assert a high pulse on reset_SM signal to start the I/O PLL dynamic phase shift reconfiguration operation.
Figure 24. Waveform Example for Dynamic Phase Shift Using IOPLL IP Core Design Example
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