Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

4.2.5.1. Design Example: Dynamic Phase Shift Using IOPLL IP Core

This design example uses the same design as "Design Example 3: Dynamic Phase Shift Using IOPLL Reconfig IP Core" without using the IOPLL Reconfig Intel® FPGA IP core. This design example demonstrates the implementation of the I/O PLL dynamic phase shift directly through the IOPLL IP core.

To run the test with this design example, perform these steps:

  1. Download and restore the iopll-dynamic-phase-shift.qar file.
  2. Change the device and pin assignments of the design example to match your hardware.
  3. Recompile the design example. Ensure that the design example does not contain any timing violation after recompilation.
  4. Open the AN.stp file and program the device with top.sof.
  5. Assert a high pulse on reset_SM signal to start the I/O PLL dynamic phase shift reconfiguration operation.
Figure 24. Waveform Example for Dynamic Phase Shift Using IOPLL IP Core Design Example