Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

2.2.2. PLL Usage

fPLLs are optimized for use as transceiver transmit PLLs and for synthesizing reference clock frequencies. You can use the fPLLs to:

  • Transmit clocking for transceivers
  • Reduce the number of required oscillators on the board

I/O PLLs are optimized for use with memory interfaces and LVDS SERDES. You can use the I/O PLLs to:

  • Reduce the number of required oscillators on the board
  • Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source
  • Simplify the design of external memory interfaces and high-speed LVDS interfaces
  • Ease timing closure because the I/O PLLs are tightly coupled with the I/Os
  • Compensate for clock network delay
  • Zero delay buffering