Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

3.6. Guideline: I/O PLL Reconfiguration

To reconfigure the I/O PLL, refer to the following guidelines:

  • If the reference clock frequency changes, you must recalibrate the I/O PLL using the IOPLL Intel® FPGA IP core.
  • The I/O PLL reconfiguration interface must have a free running mgmt_clk signal. The I/O PLL dynamic phase shift interface must have a free running scanclk signal. These interfaces eliminate the need to precisely control the start and stop of mgmt_clk and scanclk signals.
  • The I/O PLL can be reconfigured with .mif streaming mode and advanced mode using the IOPLL Reconfig Intel® FPGA IP core. Intel recommends using the .mif streaming mode.
  • Use caution when reconfiguring an I/O PLL with a non-zero phase shift setting. Modifying the M counter or N counter settings does not change the relative phase shift (in percent), but alters the absolute phase shift (in picoseconds). Modifying the C counter settings does not change the absolute phase shift, but modifies the relative phase shift.