Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

4.2.3.1. Generating a New IP-XACT File

To generate a new IP-XACT file, follow these steps:

  1. On the IOPLL Intel FPGA IP dialog box, click Generate HDL.
  2. Ensure either Verilog or VHDL is selected for the Create HDL design files for synthesis option. Click Generate to generate the IP-XACT file.
The s10_iobank_pll.ipxact file is generated.