Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

2.2.4.2. Locked

The locked signal port of the IP core for each PLL is as follows:

  • fPLL—pll_locked
  • I/O PLL—locked

The lock detection circuit provides a signal to the core logic. The signal indicates when the feedback clock has locked onto the reference clock both in phase and frequency.

PLL loses lock if the input reference clock stops toggling. When PLL loses lock, the output of the PLL starts drifting out of the desired frequency. The downstream logic must be held inactive once PLL has lost lock.