Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

4.3.4.3. Design Example 3: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core

This design example uses a 1SG280LU3F50E2VGS1 device to demonstrate the implementation of the I/O PLL clock gating reconfiguration using the IOPLL Reconfig IP core. This design example consists of the IOPLL IP core, IOPLL Reconfig IP core, and In-System Sources & Probes IP core.

The I/O PLL synthesizes eight output clocks of 200 MHz each. The input reference clock is 50 MHz.

The IOPLL Reconfig IP core connects to a state machine to perform the I/O PLL clock output gating. A high pulse on the reset_SM input through the In-System Sources & Probes IP core triggers the I/O PLL reconfiguration operation. After the I/O PLL reconfiguration operation is complete, outclk0 is ungated and outclk1 is gated.

To run the test with this design example, perform these steps:

  1. Download and restore the iopll-reconfig-clock-gating.qar file.
  2. Change the device and pin assignments of the design example to match your hardware.
  3. Recompile the design example. Ensure that the design example does not contain any timing violation after recompilation.
  4. Open the AN.stp file and program the device with top.sof.
  5. Assert a high pulse on the reset_SM signal to start the I/O PLL clock gating reconfiguration operation.
Figure 28. Waveform Example for Clock Gating Reconfiguration Design Example