Visible to Intel only — GUID: xxd1489118045253
Ixiasoft
Visible to Intel only — GUID: xxd1489118045253
Ixiasoft
4.3.4.3. Design Example 3: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core
This design example uses a 1SG280LU3F50E2VGS1 device to demonstrate the implementation of the I/O PLL clock gating reconfiguration using the IOPLL Reconfig IP core. This design example consists of the IOPLL IP core, IOPLL Reconfig IP core, and In-System Sources & Probes IP core.
The I/O PLL synthesizes eight output clocks of 200 MHz each. The input reference clock is 50 MHz.
The IOPLL Reconfig IP core connects to a state machine to perform the I/O PLL clock output gating. A high pulse on the reset_SM input through the In-System Sources & Probes IP core triggers the I/O PLL reconfiguration operation. After the I/O PLL reconfiguration operation is complete, outclk0 is ungated and outclk1 is gated.
To run the test with this design example, perform these steps:
- Download and restore the iopll-reconfig-clock-gating.qar file.
- Change the device and pin assignments of the design example to match your hardware.
- Recompile the design example. Ensure that the design example does not contain any timing violation after recompilation.
- Open the AN.stp file and program the device with top.sof.
- Assert a high pulse on the reset_SM signal to start the I/O PLL clock gating reconfiguration operation.