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1. Stratix® 10 Clocking and PLL Overview
2. Stratix® 10 Clocking and PLL Architecture and Features
3. Stratix® 10 Clocking and PLL Design Considerations
4. Stratix® 10 Clocking and PLL Implementation Guides
5. Clock Control Intel® FPGA IP Core References
6. IOPLL Intel® FPGA IP Core References
7. IOPLL Reconfig Intel® FPGA IP Core References
8. Stratix® 10 Clocking and PLL User Guide Archives
9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Architecture
2.2.4. PLL Control Signals
2.2.5. Clock Feedback Modes
2.2.6. Clock Multiplication and Division
2.2.7. Programmable Phase Shift
2.2.8. Programmable Duty Cycle
2.2.9. PLL Cascading
2.2.10. Clock Switchover
2.2.11. PLL Reconfiguration and Dynamic Phase Shift
2.2.12. PLL Calibration
4.3.4.1. Design Example 1: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.2. Design Example 2: Advanced Mode Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.3. Design Example 3: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.4. Design Example 4: Dynamic Phase Shift Using IOPLL Reconfig IP Core
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6.3. Dynamic Phase Shift Ports in the IOPLL IP Core
Figure 30. Dynamic Phase Shift Port Ports in the IOPLL IP Core
Port | Direction | Description | ||||||||||||||||||||||
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scanclk | Input | Dynamic phase shift clock that drives the IOPLL IP core dynamic phase shift operation. This port must be connected to a valid clock source. The maximum input clock frequency is 100 MHz. | ||||||||||||||||||||||
phase_en | Input | Active high signal. Asserts to start the dynamic phase shift operation. phase_en can only be asserted 4 clocks after phase_done assertion. | ||||||||||||||||||||||
updn | Input | Determines the direction of dynamic phase shift. When updn = 0, phase shift is in negative direction. When updn = 1, phase shift is in positive direction. | ||||||||||||||||||||||
cntsel[4..0] | Input |
Determines the counter to be selected to perform dynamic phase shift operation.
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num_phase_shift[2..0] | Input | Determines the number of phase shifts per dynamic phase shift operation. Up to seven phase shifts per operation are possible. Each phase shift step is equal to 1/8 of I/O PLL VCO period. num_phase_shift must never be set to 0 in DPS mode. | ||||||||||||||||||||||
phase_done | Output | The IOPLL IP core drives this port high for one scanclk cycle after dynamic phase shift operation is complete. |