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1. Stratix® 10 Clocking and PLL Overview
2. Stratix® 10 Clocking and PLL Architecture and Features
3. Stratix® 10 Clocking and PLL Design Considerations
4. Stratix® 10 Clocking and PLL Implementation Guides
5. Clock Control Intel® FPGA IP Core References
6. IOPLL Intel® FPGA IP Core References
7. IOPLL Reconfig Intel® FPGA IP Core References
8. Stratix® 10 Clocking and PLL User Guide Archives
9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Architecture
2.2.4. PLL Control Signals
2.2.5. Clock Feedback Modes
2.2.6. Clock Multiplication and Division
2.2.7. Programmable Phase Shift
2.2.8. Programmable Duty Cycle
2.2.9. PLL Cascading
2.2.10. Clock Switchover
2.2.11. PLL Reconfiguration and Dynamic Phase Shift
2.2.12. PLL Calibration
4.3.4.1. Design Example 1: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.2. Design Example 2: Advanced Mode Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.3. Design Example 3: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.4. Design Example 4: Dynamic Phase Shift Using IOPLL Reconfig IP Core
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7.2.1.2. Data Bus Setting for Ripplecap
Multiply Factor 13 | Ripplecap Setting Address = 00001010 Data [2:1] |
---|---|
4-5 | 2'b00 |
6-15 | 2'b00 |
16-23 | 2'b10 |
24-43 | 2'b00 |
44-64 | 2'b10 |
65-124 | 2'b10 |
>124 | 2'b10 |
13 If you select the Use Nondedicated Feedback Path option under the Normal or Source Synchronous compensation mode, the Multiply Factor is M x C i , where M is M counter value while C i is the Compensated Outclk C counter value. Else, the Multiply Factor is only the M counter value.