Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

4.2. IOPLL Intel® FPGA IP Core

The IOPLL IP core allows you to configure the settings of the Stratix® 10 I/O PLL.

The IOPLL IP core supports the following features:

  • Supports six different clock feedback modes: direct, external feedback, normal, source synchronous, zero delay buffer, and LVDS mode.
  • Generates up to nine clock output signals for the Stratix® 10 device.
  • Switches between two reference input clocks.
  • Supports adjacent PLL (adjpllin) input to connect with an upstream PLL in PLL cascading mode.
  • Generates the Memory Initialization File (.mif) and allows PLL dynamic reconfiguration.
  • Supports PLL dynamic phase shift.