Stratix® 10 Clocking and PLL User Guide

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ID 683195
Date 7/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Clocking and PLL Overview 2. Stratix® 10 Clocking and PLL Architecture and Features 3. Stratix® 10 Clocking and PLL Design Considerations 4. Stratix® 10 Clocking and PLL Implementation Guides 5. Clock Control Intel® FPGA IP Core References 6. IOPLL Intel® FPGA IP Core References 7. IOPLL Reconfig Intel® FPGA IP Core References 8. Stratix® 10 Clocking and PLL User Guide Archives 9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide
1. Stratix® 10 Clocking and PLL Overview x
1.1. Clock Networks Overview 1.2. PLLs Overview
2. Stratix® 10 Clocking and PLL Architecture and Features x
2.1. Clock Networks Architecture and Features 2.2. PLLs Architecture and Features
2.1. Clock Networks Architecture and Features x
2.1.1. Clock Network Architecture 2.1.2. Clock Resources 2.1.3. Programmable Clock Routing Sources 2.1.4. Clock Control Features
2.1.1. Clock Network Architecture x
2.1.1.1. Clock Network Hierarchy 2.1.1.2. Clock Sector 2.1.1.3. Programmable Clock Routing
2.1.3. Programmable Clock Routing Sources x
2.1.3.1. Dedicated Clock Input Pins 2.1.3.2. Internal Logic 2.1.3.3. DPA Clock Outputs 2.1.3.4. Transceiver Clock Outputs 2.1.3.5. PLL Clock Outputs
2.1.4. Clock Control Features x
2.1.4.1. Clock Gating 2.1.4.2. Clock Divider 2.1.4.3. Dynamic Clock Switchover
2.1.4.1. Clock Gating x
2.1.4.1.1. Root Clock Gate 2.1.4.1.2. Sector Clock Gate 2.1.4.1.3. I/O PLL Clock Gate 2.1.4.1.4. LAB Clock Gate
2.2. PLLs Architecture and Features x
2.2.1. PLL Features 2.2.2. PLL Usage 2.2.3. PLL Architecture 2.2.4. PLL Control Signals 2.2.5. Clock Feedback Modes 2.2.6. Clock Multiplication and Division 2.2.7. Programmable Phase Shift 2.2.8. Programmable Duty Cycle 2.2.9. PLL Cascading 2.2.10. Clock Switchover 2.2.11. PLL Reconfiguration and Dynamic Phase Shift 2.2.12. PLL Calibration
2.2.4. PLL Control Signals x
2.2.4.1. Reset 2.2.4.2. Locked
2.2.5. Clock Feedback Modes x
2.2.5.1. Direct Compensation Mode 2.2.5.2. LVDS Compensation Mode 2.2.5.3. Source Synchronous Compensation Mode 2.2.5.4. Normal Compensation Mode 2.2.5.5. Zero-Delay Buffer Mode 2.2.5.6. External Feedback Mode
2.2.10. Clock Switchover x
2.2.10.1. Automatic Switchover 2.2.10.2. Automatic Switchover with Manual Override 2.2.10.3. Manual Clock Switchover
2.2.12. PLL Calibration x
2.2.12.1. Power-Up Calibration 2.2.12.2. User Calibration
3. Stratix® 10 Clocking and PLL Design Considerations x
3.1. Guideline: Clock Switchover 3.2. IP Core Constraints 3.3. Guideline: Resetting the PLL 3.4. Guideline: Configuration Constraints 3.5. Guideline: Timing Closure 3.6. Guideline: I/O PLL Reconfiguration 3.7. Guideline: I/O PLL Jitter Performance 3.8. Guideline: Clock Gating
4. Stratix® 10 Clocking and PLL Implementation Guides x
4.1. Clock Control Intel® FPGA IP Core 4.2. IOPLL Intel® FPGA IP Core 4.3. IOPLL Reconfig Stratix® 10 FPGA IP Core
4.1. Clock Control Intel® FPGA IP Core x
4.1.1. Release Information for Clock Control Intel® FPGA IP
4.2. IOPLL Intel® FPGA IP Core x
4.2.1. Release Information for IOPLL Intel® FPGA IP 4.2.2. .mif File Generation 4.2.3. IP-XACT File Generation 4.2.4. Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core 4.2.5. Design Example
4.2.2. .mif File Generation x
4.2.2.1. Generating a New .mif File 4.2.2.2. Adding Configurations to Existing .mif File
4.2.3. IP-XACT File Generation x
4.2.3.1. Generating a New IP-XACT File
4.2.4. Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core x
4.2.4.1. I/O PLL Dynamic Phase Shift Operation
4.2.5. Design Example x
4.2.5.1. Design Example: Dynamic Phase Shift Using IOPLL IP Core
4.3. IOPLL Reconfig Stratix® 10 FPGA IP Core x
4.3.1. Release Information for IOPLL Reconfig Intel® FPGA IP 4.3.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core 4.3.3. IOPLL Reconfig IP Core Reconfiguration Modes 4.3.4. Design Examples
4.3.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core x
4.3.2.1. Connectivity between the IOPLL and IOPLL Reconfig IP Cores 4.3.2.2. Connecting the IOPLL and IOPLL Reconfig IP Cores
4.3.3. IOPLL Reconfig IP Core Reconfiguration Modes x
4.3.3.1. .mif Streaming Reconfiguration 4.3.3.2. Advanced Mode Reconfiguration 4.3.3.3. Clock Gating Reconfiguration 4.3.3.4. Dynamic Phase Shift Reconfiguration
4.3.3.1. .mif Streaming Reconfiguration x
4.3.3.1.1. Recalibration Using .mif
4.3.3.2. Advanced Mode Reconfiguration x
4.3.3.2.1. Recalibration Using Advanced Mode
4.3.4. Design Examples x
4.3.4.1. Design Example 1: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core 4.3.4.2. Design Example 2: Advanced Mode Reconfiguration Using IOPLL Reconfig IP Core 4.3.4.3. Design Example 3: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core 4.3.4.4. Design Example 4: Dynamic Phase Shift Using IOPLL Reconfig IP Core
5. Clock Control Intel® FPGA IP Core References x
5.1. Clock Control IP Core Parameters 5.2. Clock Control IP Core Ports and Signals
6. IOPLL Intel® FPGA IP Core References x
6.1. IOPLL IP Core Parameters 6.2. IOPLL IP Core Ports and Signals 6.3. Dynamic Phase Shift Ports in the IOPLL IP Core
6.1. IOPLL IP Core Parameters x
6.1.1. IOPLL IP Core Parameters - PLL Tab 6.1.2. IOPLL IP Core Parameters - Settings Tab 6.1.3. IOPLL IP Core Parameters - Cascading Tab 6.1.4. IOPLL IP Core Parameters - Dynamic Reconfiguration Tab 6.1.5. IOPLL IP Core Parameters - Advanced Parameters Tab
7. IOPLL Reconfig Intel® FPGA IP Core References x
7.1. Avalon® -MM Interface Ports in the IOPLL Reconfig IP Core 7.2. Address Bus and Data Bus Settings
7.2. Address Bus and Data Bus Settings x
7.2.1. Address Bus and Data Bus Settings for Advanced Mode Reconfiguration 7.2.2. Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration 7.2.3. Data Bus Setting for Dynamic Phase Shift for IOPLL Reconfig IP Core
7.2.1. Address Bus and Data Bus Settings for Advanced Mode Reconfiguration x
7.2.1.1. Data Bus Setting for Bandwidth Control and Charge Pump 7.2.1.2. Data Bus Setting for Ripplecap
1. Stratix® 10 Clocking and PLL Overview
2. Stratix® 10 Clocking and PLL Architecture and Features
3. Stratix® 10 Clocking and PLL Design Considerations
4. Stratix® 10 Clocking and PLL Implementation Guides
5. Clock Control Intel® FPGA IP Core References
6. IOPLL Intel® FPGA IP Core References
7. IOPLL Reconfig Intel® FPGA IP Core References
8. Stratix® 10 Clocking and PLL User Guide Archives
9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide

7.2.1. Address Bus and Data Bus Settings for Advanced Mode Reconfiguration

Table 20.  Address Bus and Data Bus Settings for Advanced Mode Reconfiguration
Register Name Address (Binary) Counter Bit Setting
M Counter High Count 00000100
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00000111
Bypass Enable 11 00000101
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 11 00000110
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
N Counter High Count 00000000
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00000010
Bypass Enable 11 00000001
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 11 00000001
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
C0 Counter High Count 00011011
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00011110
Bypass Enable 11 00011100
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 11 00011101
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
C1 Counter High Count 00011111
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00100010
Bypass Enable 11 00100000
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 11 00100001
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
C2 Counter High Count 00100011
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00100110
Bypass Enable 11 00100100
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 11 00100101
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
C3 Counter High Count 00100111
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00101010
Bypass Enable 11 00101000
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 11 00101001
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
C4 Counter High Count 00101011
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00101110
Bypass Enable 11 00101100
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 11 00101101
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
C5 Counter High Count 00101111
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00110010
Bypass Enable 11 00110000
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 11 00110001
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
C6 Counter High Count 00110011
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00110110
Bypass Enable 11 00110100
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 11 00110101
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
C7 Counter High Count 00110111
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00111010
Bypass Enable 11 00111000
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 11 00111001
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
C8 Counter High Count 00111011
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00111110
Bypass Enable 11 00111100
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 11 00111101
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
Charge Pump Current 11 Charge pump setting [2:0] 00000001
  • Data[6:4] = Charge Pump Setting [2:0]
    • Configure charge pump setting [2:0] on data bit 4 to 6.
Charge pump setting [5:3] 00001101
  • Data[7:5] = Charge Pump Setting [5:3]
    • Configure charge pump setting [5:3] on data bit 5 to 7.
Bandwidth Setting 11 — 00001010
  • Data[6:3] = Bandwidth Setting
    • Configure bandwidth setting on data bit 3 to 6.
Ripplecap Setting 11 — 00001010
  • Data[2:1] = Ripplecap Setting
    • Configure ripplecap setting on data bit 1 and 2.
Calibration 11 Calibration Request 01001001
  • Data[6] = Request Calibration
    • Data[6] = 1, to request calibration
Calibration Enable 01001010
  • Data[7:0] = Enable Calibration
    • Data[7:0] = 8’b00000011, to enable calibration

Section Content
Data Bus Setting for Bandwidth Control and Charge Pump
Data Bus Setting for Ripplecap

11 Perform a read-modify-write operation to configure this setting. PLL may lose lock and can cause reliability issue to your device if you configure with the wrong PLL setting, configure the wrong bit, or overwrite the whole byte for settings that made up just part of one byte.
Level Two Title