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1. Stratix® 10 Clocking and PLL Overview
2. Stratix® 10 Clocking and PLL Architecture and Features
3. Stratix® 10 Clocking and PLL Design Considerations
4. Stratix® 10 Clocking and PLL Implementation Guides
5. Clock Control Intel® FPGA IP Core References
6. IOPLL Intel® FPGA IP Core References
7. IOPLL Reconfig Intel® FPGA IP Core References
8. Stratix® 10 Clocking and PLL User Guide Archives
9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Architecture
2.2.4. PLL Control Signals
2.2.5. Clock Feedback Modes
2.2.6. Clock Multiplication and Division
2.2.7. Programmable Phase Shift
2.2.8. Programmable Duty Cycle
2.2.9. PLL Cascading
2.2.10. Clock Switchover
2.2.11. PLL Reconfiguration and Dynamic Phase Shift
2.2.12. PLL Calibration
4.3.4.1. Design Example 1: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.2. Design Example 2: Advanced Mode Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.3. Design Example 3: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.4. Design Example 4: Dynamic Phase Shift Using IOPLL Reconfig IP Core
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4.3.3.1. .mif Streaming Reconfiguration
.mif streaming allows you to dynamically reconfigure the I/O PLL through the IOPLL Reconfig IP core using predefined settings saved in an on-chip RAM. You must generate a .mif file containing these pre-defined configurations, up to 32 I/O PLL configurations, from the IOPLL IP core parameter editor.
To perform .mif streaming reconfiguration, follow these steps:
- Set mgmt_address[9:8] = 2’b00 to choose the .mif streaming mode and set mgmt_writedata[4:0] to the index of the desired configuration in the .mif file.
- To start the .mif streaming reconfiguration on the I/O PLL, assert the mgmt_write signal for one mgmt_clk cycle. mgmt_waitrequest is asserted by the IOPLL Reconfig IP core while .mif streaming is in progress.
- After the reconfiguration is complete, the mgmt_waitrequest signal is de-asserted.
- In the IOPLL Reconfig IP core parameter editor, select the Assert waitrequest until IOPLL has locked option for the I/O PLL to lock. Otherwise, you can wait for the I/O PLL to lock to ensure the I/O PLL reconfiguration is complete.
Recalibration is done automatically for .mif streaming reconfiguration. If you want to manually trigger recalibration using .mif file, follow the steps in the Recalibration Using .mif section.