Stratix® 10 Clocking and PLL User Guide

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ID 683195
Date 7/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Clocking and PLL Overview 2. Stratix® 10 Clocking and PLL Architecture and Features 3. Stratix® 10 Clocking and PLL Design Considerations 4. Stratix® 10 Clocking and PLL Implementation Guides 5. Clock Control Intel® FPGA IP Core References 6. IOPLL Intel® FPGA IP Core References 7. IOPLL Reconfig Intel® FPGA IP Core References 8. Stratix® 10 Clocking and PLL User Guide Archives 9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide
1. Stratix® 10 Clocking and PLL Overview x
1.1. Clock Networks Overview 1.2. PLLs Overview
2. Stratix® 10 Clocking and PLL Architecture and Features x
2.1. Clock Networks Architecture and Features 2.2. PLLs Architecture and Features
2.1. Clock Networks Architecture and Features x
2.1.1. Clock Network Architecture 2.1.2. Clock Resources 2.1.3. Programmable Clock Routing Sources 2.1.4. Clock Control Features
2.1.1. Clock Network Architecture x
2.1.1.1. Clock Network Hierarchy 2.1.1.2. Clock Sector 2.1.1.3. Programmable Clock Routing
2.1.3. Programmable Clock Routing Sources x
2.1.3.1. Dedicated Clock Input Pins 2.1.3.2. Internal Logic 2.1.3.3. DPA Clock Outputs 2.1.3.4. Transceiver Clock Outputs 2.1.3.5. PLL Clock Outputs
2.1.4. Clock Control Features x
2.1.4.1. Clock Gating 2.1.4.2. Clock Divider 2.1.4.3. Dynamic Clock Switchover
2.1.4.1. Clock Gating x
2.1.4.1.1. Root Clock Gate 2.1.4.1.2. Sector Clock Gate 2.1.4.1.3. I/O PLL Clock Gate 2.1.4.1.4. LAB Clock Gate
2.2. PLLs Architecture and Features x
2.2.1. PLL Features 2.2.2. PLL Usage 2.2.3. PLL Architecture 2.2.4. PLL Control Signals 2.2.5. Clock Feedback Modes 2.2.6. Clock Multiplication and Division 2.2.7. Programmable Phase Shift 2.2.8. Programmable Duty Cycle 2.2.9. PLL Cascading 2.2.10. Clock Switchover 2.2.11. PLL Reconfiguration and Dynamic Phase Shift 2.2.12. PLL Calibration
2.2.4. PLL Control Signals x
2.2.4.1. Reset 2.2.4.2. Locked
2.2.5. Clock Feedback Modes x
2.2.5.1. Direct Compensation Mode 2.2.5.2. LVDS Compensation Mode 2.2.5.3. Source Synchronous Compensation Mode 2.2.5.4. Normal Compensation Mode 2.2.5.5. Zero-Delay Buffer Mode 2.2.5.6. External Feedback Mode
2.2.10. Clock Switchover x
2.2.10.1. Automatic Switchover 2.2.10.2. Automatic Switchover with Manual Override 2.2.10.3. Manual Clock Switchover
2.2.12. PLL Calibration x
2.2.12.1. Power-Up Calibration 2.2.12.2. User Calibration
3. Stratix® 10 Clocking and PLL Design Considerations x
3.1. Guideline: Clock Switchover 3.2. IP Core Constraints 3.3. Guideline: Resetting the PLL 3.4. Guideline: Configuration Constraints 3.5. Guideline: Timing Closure 3.6. Guideline: I/O PLL Reconfiguration 3.7. Guideline: I/O PLL Jitter Performance 3.8. Guideline: Clock Gating
4. Stratix® 10 Clocking and PLL Implementation Guides x
4.1. Clock Control Intel® FPGA IP Core 4.2. IOPLL Intel® FPGA IP Core 4.3. IOPLL Reconfig Stratix® 10 FPGA IP Core
4.1. Clock Control Intel® FPGA IP Core x
4.1.1. Release Information for Clock Control Intel® FPGA IP
4.2. IOPLL Intel® FPGA IP Core x
4.2.1. Release Information for IOPLL Intel® FPGA IP 4.2.2. .mif File Generation 4.2.3. IP-XACT File Generation 4.2.4. Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core 4.2.5. Design Example
4.2.2. .mif File Generation x
4.2.2.1. Generating a New .mif File 4.2.2.2. Adding Configurations to Existing .mif File
4.2.3. IP-XACT File Generation x
4.2.3.1. Generating a New IP-XACT File
4.2.4. Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core x
4.2.4.1. I/O PLL Dynamic Phase Shift Operation
4.2.5. Design Example x
4.2.5.1. Design Example: Dynamic Phase Shift Using IOPLL IP Core
4.3. IOPLL Reconfig Stratix® 10 FPGA IP Core x
4.3.1. Release Information for IOPLL Reconfig Intel® FPGA IP 4.3.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core 4.3.3. IOPLL Reconfig IP Core Reconfiguration Modes 4.3.4. Design Examples
4.3.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core x
4.3.2.1. Connectivity between the IOPLL and IOPLL Reconfig IP Cores 4.3.2.2. Connecting the IOPLL and IOPLL Reconfig IP Cores
4.3.3. IOPLL Reconfig IP Core Reconfiguration Modes x
4.3.3.1. .mif Streaming Reconfiguration 4.3.3.2. Advanced Mode Reconfiguration 4.3.3.3. Clock Gating Reconfiguration 4.3.3.4. Dynamic Phase Shift Reconfiguration
4.3.3.1. .mif Streaming Reconfiguration x
4.3.3.1.1. Recalibration Using .mif
4.3.3.2. Advanced Mode Reconfiguration x
4.3.3.2.1. Recalibration Using Advanced Mode
4.3.4. Design Examples x
4.3.4.1. Design Example 1: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core 4.3.4.2. Design Example 2: Advanced Mode Reconfiguration Using IOPLL Reconfig IP Core 4.3.4.3. Design Example 3: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core 4.3.4.4. Design Example 4: Dynamic Phase Shift Using IOPLL Reconfig IP Core
5. Clock Control Intel® FPGA IP Core References x
5.1. Clock Control IP Core Parameters 5.2. Clock Control IP Core Ports and Signals
6. IOPLL Intel® FPGA IP Core References x
6.1. IOPLL IP Core Parameters 6.2. IOPLL IP Core Ports and Signals 6.3. Dynamic Phase Shift Ports in the IOPLL IP Core
6.1. IOPLL IP Core Parameters x
6.1.1. IOPLL IP Core Parameters - PLL Tab 6.1.2. IOPLL IP Core Parameters - Settings Tab 6.1.3. IOPLL IP Core Parameters - Cascading Tab 6.1.4. IOPLL IP Core Parameters - Dynamic Reconfiguration Tab 6.1.5. IOPLL IP Core Parameters - Advanced Parameters Tab
7. IOPLL Reconfig Intel® FPGA IP Core References x
7.1. Avalon® -MM Interface Ports in the IOPLL Reconfig IP Core 7.2. Address Bus and Data Bus Settings
7.2. Address Bus and Data Bus Settings x
7.2.1. Address Bus and Data Bus Settings for Advanced Mode Reconfiguration 7.2.2. Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration 7.2.3. Data Bus Setting for Dynamic Phase Shift for IOPLL Reconfig IP Core
7.2.1. Address Bus and Data Bus Settings for Advanced Mode Reconfiguration x
7.2.1.1. Data Bus Setting for Bandwidth Control and Charge Pump 7.2.1.2. Data Bus Setting for Ripplecap
1. Stratix® 10 Clocking and PLL Overview
2. Stratix® 10 Clocking and PLL Architecture and Features
3. Stratix® 10 Clocking and PLL Design Considerations
4. Stratix® 10 Clocking and PLL Implementation Guides
5. Clock Control Intel® FPGA IP Core References
6. IOPLL Intel® FPGA IP Core References
7. IOPLL Reconfig Intel® FPGA IP Core References
8. Stratix® 10 Clocking and PLL User Guide Archives
9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide

7.1. Avalon® -MM Interface Ports in the IOPLL Reconfig IP Core

Table 19.   Avalon® -MM Interface Ports in the IOPLL Reconfig IP Core for Stratix® 10 Devices
Port Direction Description
mgmt_clk Input Dynamic reconfiguration clock that drives the IOPLL Reconfig IP core. The maximum input clock frequency is 100 MHz. This clock can be an independent clock source. It must be free running, which means it cannot be connected to the output of the I/O PLL being reconfigured.
mgmt_reset Input Active high signal. Synchronous reset input to clear all the data in the IOPLL Reconfig IP core.
mgmt_waitrequest Output This port goes high when PLL reconfiguration process started and remains high during PLL reconfiguration. After PLL reconfiguration process completed, this port goes low.
mgmt_write Input Active high signal. Asserts to indicate a write operation.
mgmt_read Input Active high signal. Asserts to indicate a read operation.
mgmt_writedata[7..0] Input Writes data to this port when mgmt_write signal is asserted.
mgmt_readdata[7..0] Output Reads data from this port when mgmt_read signal is asserted.
mgmt_address[9..0] Input Specifies the address of the data bus for a read or write operation.
reconfig_from_pll[10..0] Input Bus that connects to reconfig_from_pll[10..0] bus in the IOPLL Intel® FPGA IP core.
reconfig_to_pll[29..0] Output Bus that connects to reconfig_to_pll[29..0] bus in the IOPLL IP core.
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