Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 7/11/2024
Public
Document Table of Contents

4.3.4.1. Design Example 1: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core

This design example uses a 1SG280LU3F50E2VGS1 device to demonstrate the implementation of the I/O PLL reconfiguration through .mif streaming using the IOPLL Reconfig IP core. This design example consists of the IOPLL IP core, IOPLL Reconfig IP core, and In-System Sources & Probes Intel® FPGA IP core.

The I/O PLL synthesizes two output clocks of 400 MHz with 0 ps phase shift and 200 MHz with 0 ps phase shift on counter C0 output and counter C1 output respectively at medium bandwidth. The input reference clock is 50 MHz.

The IOPLL Reconfig IP core connects to a state machine to perform the I/O PLL .mif streaming reconfiguration operation. A high pulse on the reset_SM input through the In-System Sources & Probes IP core triggers the I/O PLL reconfiguration operation. After the I/O PLL reconfiguration operation is complete, the I/O PLL operates in the following configuration at medium bandwidth:

  • 100 MHz with 0 ps phase shift on counter C0 output
  • 100 MHz with 0 ps phase shift on counter C1 output

To run the test with this design example, perform these steps:

  1. Download and restore the iopll-reconfig-mif-streaming.qar file.
  2. Change the device and pin assignments of the design example to match your hardware.
  3. Recompile the design example. Ensure that the design example does not contain any timing violation after recompilation.
  4. Open the AN.stp file and program the device with top.sof.
  5. Assert a high pulse on the reset_SM signal to start the I/O PLL reconfiguration operation.
Figure 26. Waveform Example for .mif Streaming Reconfiguration Design Example