Stratix® 10 Clocking and PLL User Guide

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ID 683195
Date 7/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Clocking and PLL Overview 2. Stratix® 10 Clocking and PLL Architecture and Features 3. Stratix® 10 Clocking and PLL Design Considerations 4. Stratix® 10 Clocking and PLL Implementation Guides 5. Clock Control Intel® FPGA IP Core References 6. IOPLL Intel® FPGA IP Core References 7. IOPLL Reconfig Intel® FPGA IP Core References 8. Stratix® 10 Clocking and PLL User Guide Archives 9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide
1. Stratix® 10 Clocking and PLL Overview x
1.1. Clock Networks Overview 1.2. PLLs Overview
2. Stratix® 10 Clocking and PLL Architecture and Features x
2.1. Clock Networks Architecture and Features 2.2. PLLs Architecture and Features
2.1. Clock Networks Architecture and Features x
2.1.1. Clock Network Architecture 2.1.2. Clock Resources 2.1.3. Programmable Clock Routing Sources 2.1.4. Clock Control Features
2.1.1. Clock Network Architecture x
2.1.1.1. Clock Network Hierarchy 2.1.1.2. Clock Sector 2.1.1.3. Programmable Clock Routing
2.1.3. Programmable Clock Routing Sources x
2.1.3.1. Dedicated Clock Input Pins 2.1.3.2. Internal Logic 2.1.3.3. DPA Clock Outputs 2.1.3.4. Transceiver Clock Outputs 2.1.3.5. PLL Clock Outputs
2.1.4. Clock Control Features x
2.1.4.1. Clock Gating 2.1.4.2. Clock Divider 2.1.4.3. Dynamic Clock Switchover
2.1.4.1. Clock Gating x
2.1.4.1.1. Root Clock Gate 2.1.4.1.2. Sector Clock Gate 2.1.4.1.3. I/O PLL Clock Gate 2.1.4.1.4. LAB Clock Gate
2.2. PLLs Architecture and Features x
2.2.1. PLL Features 2.2.2. PLL Usage 2.2.3. PLL Architecture 2.2.4. PLL Control Signals 2.2.5. Clock Feedback Modes 2.2.6. Clock Multiplication and Division 2.2.7. Programmable Phase Shift 2.2.8. Programmable Duty Cycle 2.2.9. PLL Cascading 2.2.10. Clock Switchover 2.2.11. PLL Reconfiguration and Dynamic Phase Shift 2.2.12. PLL Calibration
2.2.4. PLL Control Signals x
2.2.4.1. Reset 2.2.4.2. Locked
2.2.5. Clock Feedback Modes x
2.2.5.1. Direct Compensation Mode 2.2.5.2. LVDS Compensation Mode 2.2.5.3. Source Synchronous Compensation Mode 2.2.5.4. Normal Compensation Mode 2.2.5.5. Zero-Delay Buffer Mode 2.2.5.6. External Feedback Mode
2.2.10. Clock Switchover x
2.2.10.1. Automatic Switchover 2.2.10.2. Automatic Switchover with Manual Override 2.2.10.3. Manual Clock Switchover
2.2.12. PLL Calibration x
2.2.12.1. Power-Up Calibration 2.2.12.2. User Calibration
3. Stratix® 10 Clocking and PLL Design Considerations x
3.1. Guideline: Clock Switchover 3.2. IP Core Constraints 3.3. Guideline: Resetting the PLL 3.4. Guideline: Configuration Constraints 3.5. Guideline: Timing Closure 3.6. Guideline: I/O PLL Reconfiguration 3.7. Guideline: I/O PLL Jitter Performance 3.8. Guideline: Clock Gating
4. Stratix® 10 Clocking and PLL Implementation Guides x
4.1. Clock Control Intel® FPGA IP Core 4.2. IOPLL Intel® FPGA IP Core 4.3. IOPLL Reconfig Stratix® 10 FPGA IP Core
4.1. Clock Control Intel® FPGA IP Core x
4.1.1. Release Information for Clock Control Intel® FPGA IP
4.2. IOPLL Intel® FPGA IP Core x
4.2.1. Release Information for IOPLL Intel® FPGA IP 4.2.2. .mif File Generation 4.2.3. IP-XACT File Generation 4.2.4. Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core 4.2.5. Design Example
4.2.2. .mif File Generation x
4.2.2.1. Generating a New .mif File 4.2.2.2. Adding Configurations to Existing .mif File
4.2.3. IP-XACT File Generation x
4.2.3.1. Generating a New IP-XACT File
4.2.4. Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core x
4.2.4.1. I/O PLL Dynamic Phase Shift Operation
4.2.5. Design Example x
4.2.5.1. Design Example: Dynamic Phase Shift Using IOPLL IP Core
4.3. IOPLL Reconfig Stratix® 10 FPGA IP Core x
4.3.1. Release Information for IOPLL Reconfig Intel® FPGA IP 4.3.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core 4.3.3. IOPLL Reconfig IP Core Reconfiguration Modes 4.3.4. Design Examples
4.3.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core x
4.3.2.1. Connectivity between the IOPLL and IOPLL Reconfig IP Cores 4.3.2.2. Connecting the IOPLL and IOPLL Reconfig IP Cores
4.3.3. IOPLL Reconfig IP Core Reconfiguration Modes x
4.3.3.1. .mif Streaming Reconfiguration 4.3.3.2. Advanced Mode Reconfiguration 4.3.3.3. Clock Gating Reconfiguration 4.3.3.4. Dynamic Phase Shift Reconfiguration
4.3.3.1. .mif Streaming Reconfiguration x
4.3.3.1.1. Recalibration Using .mif
4.3.3.2. Advanced Mode Reconfiguration x
4.3.3.2.1. Recalibration Using Advanced Mode
4.3.4. Design Examples x
4.3.4.1. Design Example 1: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core 4.3.4.2. Design Example 2: Advanced Mode Reconfiguration Using IOPLL Reconfig IP Core 4.3.4.3. Design Example 3: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core 4.3.4.4. Design Example 4: Dynamic Phase Shift Using IOPLL Reconfig IP Core
5. Clock Control Intel® FPGA IP Core References x
5.1. Clock Control IP Core Parameters 5.2. Clock Control IP Core Ports and Signals
6. IOPLL Intel® FPGA IP Core References x
6.1. IOPLL IP Core Parameters 6.2. IOPLL IP Core Ports and Signals 6.3. Dynamic Phase Shift Ports in the IOPLL IP Core
6.1. IOPLL IP Core Parameters x
6.1.1. IOPLL IP Core Parameters - PLL Tab 6.1.2. IOPLL IP Core Parameters - Settings Tab 6.1.3. IOPLL IP Core Parameters - Cascading Tab 6.1.4. IOPLL IP Core Parameters - Dynamic Reconfiguration Tab 6.1.5. IOPLL IP Core Parameters - Advanced Parameters Tab
7. IOPLL Reconfig Intel® FPGA IP Core References x
7.1. Avalon® -MM Interface Ports in the IOPLL Reconfig IP Core 7.2. Address Bus and Data Bus Settings
7.2. Address Bus and Data Bus Settings x
7.2.1. Address Bus and Data Bus Settings for Advanced Mode Reconfiguration 7.2.2. Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration 7.2.3. Data Bus Setting for Dynamic Phase Shift for IOPLL Reconfig IP Core
7.2.1. Address Bus and Data Bus Settings for Advanced Mode Reconfiguration x
7.2.1.1. Data Bus Setting for Bandwidth Control and Charge Pump 7.2.1.2. Data Bus Setting for Ripplecap
1. Stratix® 10 Clocking and PLL Overview
2. Stratix® 10 Clocking and PLL Architecture and Features
3. Stratix® 10 Clocking and PLL Design Considerations
4. Stratix® 10 Clocking and PLL Implementation Guides
5. Clock Control Intel® FPGA IP Core References
6. IOPLL Intel® FPGA IP Core References
7. IOPLL Reconfig Intel® FPGA IP Core References
8. Stratix® 10 Clocking and PLL User Guide Archives
9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide

6.1.1. IOPLL IP Core Parameters - PLL Tab

Table 12.   IOPLL IP Core Parameters - PLL Tab for Stratix® 10 Devices
Parameter Legal Value Description
Device Family Stratix® 10 Specifies the device family.
Component — Specifies the targeted device.
Speed Grade — Specifies the speed grade for targeted device.
PLL Mode Integer-N PLL Specifies the mode used for the IOPLL IP core. The only legal selection is Integer-N PLL.
Reference Clock Frequency — Specifies the input frequency for the input clock, refclk, in MHz. The default value is 100.0 MHz. The minimum and maximum value is dependent on the selected device.
My reference clock frequency might change Turn on or Turn off Select this option if you expect the reference clock frequency to change at runtime. 5
Enable Locked Output Port Turn on or Turn off Turn on to enable the locked port.
Enable physical output clock parameters Turn on or Turn off Turn on to enter physical PLL counter parameters instead of specifying a desired output clock frequency.
Operation Mode direct, external feedback, normal, source synchronous, zero delay buffer, or lvds Specifies the operation of the PLL. The default operation is direct mode.
  • If you select the direct mode, the PLL minimizes the length of the feedback path to produce the smallest possible jitter at the PLL output. The internal-clock and external-clock outputs of the PLL are phase-shifted with respect to the PLL clock input. In this mode, the PLL does not compensate for any clock networks.
  • If you select the external feedback mode, you must connect the fbclk input port to an input pin. A board-level connection must connect both the input pin and external clock output port, fboutclk. The fbclk port is aligned with the input clock.
  • If you select the normal mode, the PLL compensates for the delay of the internal clock network used by the clock output. If the PLL is also used to drive an external clock output pin, a corresponding phase shift of the signal on the output pin occurs.
  • If you select the source synchronous mode, the clock delay from pin to I/O input register matches the data delay from pin to I/O input register.
  • If you select the zero delay buffer mode, the PLL must feed an external clock output pin and compensate for the delay introduced by that pin. The signal observed on the pin is synchronized to the input clock. The PLL clock output connects to the altbidir port and drives zdbfbclk as an output port. If the PLL also drives the internal clock network, a corresponding phase shift of that network occurs.
  • If you select the lvds mode, the same data and clock timing relationship of the pins at the internal SERDES capture register is maintained. The mode compensates for the delays in LVDS clock network, and between the data pin and clock input pin to the SERDES capture register paths.
Compensated Outclk 6 0–8 Allows you to select which output clock (outclk) to be compensated. The feedback mode compensates for the clock network delay of the outclk selected. This feedback mode ensures correct phase relationship between I/O PLL input and output clocks only for the selected outclk.
Use Nondedicated Feedback Path 6 Turn on or Turn off Turn on to conserve clock resources and improve timing analysis. However, this feature creates frequency limitations and disables phase shift.
Number of Clocks 1–9 Specifies the number of output clocks required for each device in the PLL design. The requested settings for output frequency, phase shift, and duty cycle are shown based on the number of clocks selected.
Multiply Factor (M-Counter) 7 4–160 Specifies the multiply factor of M-counter.
Divide Factor (N-Counter) 7 1–110 Specifies the divide factor of N-counter.
Specify VCO Frequency Turn on or Turn off Allows you to restrict the VCO frequency to the specified value. This is useful when creating a PLL for LVDS external mode, or if a specific dynamic phase shift step size is desired.
VCO Frequency 8 —
  • When Enable physical output clock parameters is turned on—displays the VCO frequency based on the values for Reference Clock Frequency, Multiply Factor (M-Counter), and Divide Factor (N-Counter).
  • When Enable physical output clock parameters is turned off—allows you to specify the requested value for the VCO frequency. The default value is 600.0 MHz.
Give clock global name Turn on or Turn off Allows you to rename the output clock name.
Clock Name — The user clock name for Synopsis Design Constraints (SDC).
Divide Factor (C-Counter) 7 1-510 Specifies the divide factor for the output clock (C-counter).
Desired Frequency — Specifies the output clock frequency of the corresponding output clock port, outclk[], in MHz. The default value is 100.0 MHz. The minimum and maximum values depend on the device used. The PLL only reads the numerals in the first six decimal places.
Actual Frequency — Allows you to select the actual output clock frequency from a list of achievable frequencies. The default value is the closest achievable frequency to the desired frequency.
Phase Shift units ps or degrees Specifies the phase shift unit for the corresponding output clock port, outclk[], in picoseconds (ps) or degrees.
Desired Phase Shift — Specifies the requested value for the phase shift. The default value is 0 ps.
Actual Phase Shift — Allows you to select the actual phase shift from a list of achievable phase shift values. The default value is the closest achievable phase shift to the desired phase shift.
Desired Duty Cycle 0.0–100.0 Specifies the requested value for the duty cycle. The default value is 50.0%.
Actual Duty Cycle — Allows you to select the actual duty cycle from a list of achievable duty cycle values. The default value is the closest achievable duty cycle to the desired duty cycle.
Related Information
5 Enable this option if there is a deviation of 10% or more of the reference clock frequency. If this option is enabled, you must perform PLL recalibration even if the PLL settings are unchanged. For more information on recalibration using .mif, refer to the .mif Streaming Reconfiguration section.
6 This option is only available when either normal or source synchronous mode is selected.
7 This parameter is only available when Enable physical output clock parameters is turned on.
8 This parameter is only available when Enable physical output clock parameters is turned off.
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