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1. Stratix® 10 Clocking and PLL Overview
2. Stratix® 10 Clocking and PLL Architecture and Features
3. Stratix® 10 Clocking and PLL Design Considerations
4. Stratix® 10 Clocking and PLL Implementation Guides
5. Clock Control Intel® FPGA IP Core References
6. IOPLL Intel® FPGA IP Core References
7. IOPLL Reconfig Intel® FPGA IP Core References
8. Stratix® 10 Clocking and PLL User Guide Archives
9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Architecture
2.2.4. PLL Control Signals
2.2.5. Clock Feedback Modes
2.2.6. Clock Multiplication and Division
2.2.7. Programmable Phase Shift
2.2.8. Programmable Duty Cycle
2.2.9. PLL Cascading
2.2.10. Clock Switchover
2.2.11. PLL Reconfiguration and Dynamic Phase Shift
2.2.12. PLL Calibration
4.3.4.1. Design Example 1: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.2. Design Example 2: Advanced Mode Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.3. Design Example 3: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.4. Design Example 4: Dynamic Phase Shift Using IOPLL Reconfig IP Core
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6.1.3. IOPLL IP Core Parameters - Cascading Tab
Parameter | Legal Value | Description |
---|---|---|
Create a ‘cascade out’ signal to connect with a downstream PLL | Turn on or Turn off | Turn on to create the cascade_out port, which indicates that this PLL is a source and connects with a destination (downstream) PLL. |
Specifies which outclk to be used as cascading source | 0-8 | Specifies the cascading source. |
Create an adjpllin or cclk signal to connect with an upstream PLL | Turn on or Turn off | Turn on to create an input port, which indicates that this PLL is a destination and connects with a source (upstream) PLL. |
Create a permit_cal signal to connect with an upstream PLL | Turn on or Turn off | Turn on to create an input port to enable destination (downstream) PLL power-up calibration. Connect source (upstream) PLL locked signal to this input port. |
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