Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

6.1.4.4. PMA Reconfiguration Interface Signals

Table 63.  PMA Reconfiguration Interface Signals
Port Name Direction Description
reconfig_clk Input Reconfiguration interface clock. The clock frequency is 100 - 125 MHz.
reconfig_reset Input Reconfiguration interface reset. You must ensure that this active high reset signal receives a power-on reset to initialize your device.
reconfig_address[17:0] Input

Reconfiguration interface address.

Kp = Ceiling(log2(N))

Upper address bits are for shared PMA decoding if more than one PMA exist.

reconfg_byteenable[3:0] Input Reconfiguration byte enable. If byteenable[3:0] is 4'b1111, use 32-bit Dword access, otherwise use byte access.
reconfig_write Input Reconfiguration write.
reconfig_read Input Reconfiguration read.
reconfig_writedata[31:0] Input Reconfiguration write data.
reconfig_readdata[31:0] Output Reconfiguration read data.
reconfig_readdata_valid Output Reconfiguration read data valid. Optional port, only available if the port is enabled in the parameter editor.
reconfig_waitrequest Output Reconfiguration wait request.

For more information on PMA registers, refer to GTS PMA and FEC Direct PHY Soft CSR Register Map.