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1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
11. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
A. Ethernet Frame Format
B. Simulation Parameters
4.1.1. MAC Architecture
4.1.2. MAC Interfaces
4.1.3. MAC Transmit Datapath
4.1.4. MAC Receive Datapath
4.1.5. MAC Transmit and Receive Latencies
4.1.6. FIFO Buffer Thresholds
4.1.7. Congestion and Flow Control
4.1.8. Magic Packets
4.1.9. MAC Local Loopback
4.1.10. MAC Reset
4.1.11. PHY Management (MDIO)
4.1.12. Connecting MAC to External PHYs
6.1.1. 10/100/1000 Ethernet MAC Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals
6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.6. 1000BASE-X/SGMII PCS Signals
6.1.7. 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.1.1. Clock and Reset Signals
6.1.1.2. Clock Enabler Signals
6.1.1.3. MAC Control Interface Signals
6.1.1.4. MAC Status Signals
6.1.1.5. MAC Receive Interface Signals
6.1.1.6. MAC Transmit Interface Signals
6.1.1.7. Pause and Magic Packet Signals
6.1.1.8. MII/GMII/RGMII Signals
6.1.1.9. PHY Management Signals
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6.1.4.4. PMA Reconfiguration Interface Signals
Port Name | Direction | Description |
---|---|---|
reconfig_clk | Input | Reconfiguration interface clock. The clock frequency is 100 - 125 MHz. |
reconfig_reset | Input | Reconfiguration interface reset. You must ensure that this active high reset signal receives a power-on reset to initialize your device. |
reconfig_address[17:0] | Input | Reconfiguration interface address. Kp = Ceiling(log2(N)) Upper address bits are for shared PMA decoding if more than one PMA exist. |
reconfg_byteenable[3:0] | Input | Reconfiguration byte enable. If byteenable[3:0] is 4'b1111, use 32-bit Dword access, otherwise use byte access. |
reconfig_write | Input | Reconfiguration write. |
reconfig_read | Input | Reconfiguration read. |
reconfig_writedata[31:0] | Input | Reconfiguration write data. |
reconfig_readdata[31:0] | Output | Reconfiguration read data. |
reconfig_readdata_valid | Output | Reconfiguration read data valid. Optional port, only available if the port is enabled in the parameter editor. |
reconfig_waitrequest | Output | Reconfiguration wait request. |
For more information on PMA registers, refer to GTS PMA and FEC Direct PHY Soft CSR Register Map.
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