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1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
11. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
A. Ethernet Frame Format
B. Simulation Parameters
4.1.1. MAC Architecture
4.1.2. MAC Interfaces
4.1.3. MAC Transmit Datapath
4.1.4. MAC Receive Datapath
4.1.5. MAC Transmit and Receive Latencies
4.1.6. FIFO Buffer Thresholds
4.1.7. Congestion and Flow Control
4.1.8. Magic Packets
4.1.9. MAC Local Loopback
4.1.10. MAC Reset
4.1.11. PHY Management (MDIO)
4.1.12. Connecting MAC to External PHYs
6.1.1. 10/100/1000 Ethernet MAC Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals
6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.6. 1000BASE-X/SGMII PCS Signals
6.1.7. 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.1.1. Clock and Reset Signals
6.1.1.2. Clock Enabler Signals
6.1.1.3. MAC Control Interface Signals
6.1.1.4. MAC Status Signals
6.1.1.5. MAC Receive Interface Signals
6.1.1.6. MAC Transmit Interface Signals
6.1.1.7. Pause and Magic Packet Signals
6.1.1.8. MII/GMII/RGMII Signals
6.1.1.9. PHY Management Signals
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B.1. Functionality Configuration Parameters
You can use these parameters to enable or disable specific functionality in the MAC and PCS.
Parameter | Description | Default |
---|---|---|
Supported in configurations that contain the 10/100/1000 Ethernet MAC | ||
ETH_MODE | 10: Enables MII. 100: Enables MII. 1000: Enables GMII. |
1000 |
HD_ENA | Sets the HD_ENA bit in the command_config register. See Command_Config Register (Dword Offset 0x02). | 0 |
TB_MACPAUSEQ | Sets the pause_quant register. See Base Configuration Registers (Dword Offset 0x00 – 0x17). | 15 |
TB_MACIGNORE_PAUSE | Sets the PAUSE_IGNORE bit in the command_config register. See Command_Config Register (Dword Offset 0x02). | 0 |
TB_MACFWD_PAUSE | Sets the PAUSE_FWD bit in the command_config register. See Command_Config Register (Dword Offset 0x02). | 0 |
TB_MACFWD_CRC | Sets the CRC_FWD bit in the command_config register. See Command_Config Register (Dword Offset 0x02). | 0 |
TB_MACINSERT_ADDR | Sets the ADDR_INS bit in the command_config register. See Command_Config Register (Dword Offset 0x02). | 0 |
TB_PROMIS_ENA | Sets the PROMIS_EN bit in the command_config register. See Command_Config Register (Dword Offset 0x02). | 1 |
TB_MACPADEN | Sets the PAD_EN bit in the command_config register. See Command_Config Register (Dword Offset 0x02). | 1 |
TB_MACLENMAX | Maximum frame length. | 1518 |
TB_IPG_LENGTH | Sets the tx_ipg_length register. See Base Configuration Registers (Dword Offset 0x00 – 0x17). | 12 |
TB_MDIO_ADDR0 | Sets the mdio_addr0 register. See Base Configuration Registers (Dword Offset 0x00 – 0x17). | 0 |
TB_MDIO_ADDR1 | Sets the mdio_addr1 register. See Base Configuration Registers (Dword Offset 0x00 – 0x17). | 1 |
TX_FIFO_AE | Sets the tx_almost_empty register. See Base Configuration Registers (Dword Offset 0x00 – 0x17). | 8 |
TX_FIFO_AF | Sets the tx_almost_full register. See Base Configuration Registers (Dword Offset 0x00 – 0x17). | 10 |
RX_FIFO_AE | Sets the rx_almost_empty register. See Base Configuration Registers (Dword Offset 0x00 – 0x17). | 8 |
RX_FIFO_AF | Sets the rx_almost_full register. See Base Configuration Registers (Dword Offset 0x00 – 0x17). | 8 |
TX_FIFO_SECTION_EMPTY | Sets the tx_section_empty register. See Base Configuration Registers (Dword Offset 0x00 – 0x17). | 16 |
TX_FIFO_SECTION_FULL | Sets the tx_section_full register. See Base Configuration Registers (Dword Offset 0x00 – 0x17). | 16 |
RX_FIFO_SECTION_EMPTY | Sets the rx_section_empty register. See Base Configuration Registers (Dword Offset 0x00 – 0x17). | 0 |
RX_FIFO_SECTION_FULL | Sets the rx_section_full register. See Base Configuration Registers (Dword Offset 0x00 – 0x17). | 16 |
MCAST_TABLEN | Specifies the first n addresses from MCAST_ADDRESSLIST from which multicast address is selected. | 9 |
MCAST_ADDRESSLIST | A list of multicast addresses. | 0x887654332211 0x886644352611 0xABCDEF012313 0x92456545AB15 0x432680010217 0xADB589215439 0xFFEACFE3434B 0xFFCCDDAA3123 0xADB358415439 |
Supported in configurations that contain the 1000BASE-X/SGMII PCS | ||
TB_SGMII_ENA | Sets the SGMII_ENA bit in the if_mode register. See If_Mode Register (Word Offset 0x14). | 0 |
TB_SGMII_AUTO_CONF | Sets the USE_GMII_AN bit in the if_mode register. See If_Mode Register (Word Offset 0x14). | 0 |