Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

6.1.7.3. TBI Interface Signals

If the core variation does not include an embedded PMA, the PCS block provides a 62.5-MHz 2 ten-bit interface (TBI) to an external SERDES chip.
Table 75.  TBI Interface Signals for External SERDES Chip
Name I/O Description
tbi2x_tx_d[19:0] O 2X TBI transmit data. The PCS function transmits data on this bus synchronous to tbi2x_tx_clk.
tbi2x_tx_clk I 62.5-MHz TBI transmit clock from external SERDES, typically sourced by the local reference clock oscillator.
tbi2x_rx_clk I 62.5-MHz TBI receive clock from external SERDES, typically sourced by the clock recovered from the encoded serial data.
tbi2x_rx_d[19:0] I 2X TBI receive data. This bus carries the data from the external SERDES. Synchronize the bus with tbi2x_rx_clk.