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1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
11. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
A. Ethernet Frame Format
B. Simulation Parameters
4.1.1. MAC Architecture
4.1.2. MAC Interfaces
4.1.3. MAC Transmit Datapath
4.1.4. MAC Receive Datapath
4.1.5. MAC Transmit and Receive Latencies
4.1.6. FIFO Buffer Thresholds
4.1.7. Congestion and Flow Control
4.1.8. Magic Packets
4.1.9. MAC Local Loopback
4.1.10. MAC Reset
4.1.11. PHY Management (MDIO)
4.1.12. Connecting MAC to External PHYs
6.1.1. 10/100/1000 Ethernet MAC Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals
6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.6. 1000BASE-X/SGMII PCS Signals
6.1.7. 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.1.1. Clock and Reset Signals
6.1.1.2. Clock Enabler Signals
6.1.1.3. MAC Control Interface Signals
6.1.1.4. MAC Status Signals
6.1.1.5. MAC Receive Interface Signals
6.1.1.6. MAC Transmit Interface Signals
6.1.1.7. Pause and Magic Packet Signals
6.1.1.8. MII/GMII/RGMII Signals
6.1.1.9. PHY Management Signals
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9.2. Testbench Components
The testbench comprises the following modules:
- Device under test (DUT)—Your custom IP variation
- Avalon streaming Ethernet frame generator—Simulates a user application connected to the MAC system-side interface. It generates frames on the Avalon streaming transmit interface.
- Avalon streaming Ethernet frame monitor—Simulates a user application receiving frames from the MAC system-side interface. It monitors the Avalon streaming receive interface and decodes all data received.
- MII/RGMII/GMII Ethernet frame generator—Simulates a MAC function that sends frames to the PCS function.
- MII/RGMII/GMII Ethernet frame monitor—Simulates a MAC function that receives frames from the PCS function and decodes them.
- Clock and reset generator.
Configuration | System-Side Interface | Ethernet-Side Interface | Frame Generator | Frame Monitor |
---|---|---|---|---|
MAC only | Avalon® streaming interface | GMII/MII/RGMII | Avalon streaming frame generator | Avalon streaming frame monitor |
MAC with PCS | Avalon® streaming interface | TBI | Avalon streaming frame generator | Avalon streaming frame monitor |
MAC with 2XTBI PCS and embedded PMA (GTS)
Note: VHDL testbench simulation is not supported for this variant.
|
Avalon® streaming interface | 1.25 Gbps | Avalon streaming frame generator | Avalon streaming frame monitor |
PCS only | GMII/MII | TBI | GMII/MII frame generator | GMII/MII frame monitor |